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/Zephyr-latest/dts/arm/xilinx/
Dzynqmp_rpu.dtsi11 #address-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <1>;
33 local-ipi-id = <1>;
37 reg = <0xff990200 0x20>,
38 <0xff990220 0x20>,
39 <0xff990040 0x20>,
40 <0xff990060 0x20>;
49 reg = <0xff990260 0x20>,
50 <0xff990280 0x20>,
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dra2xx.dtsi16 #address-cells = <1>;
35 reg = <0x40040000 0x20>;
45 reg = <0x40040020 0x20>;
46 port = <1>;
55 reg = <0x40040040 0x20>;
65 reg = <0x40040060 0x20>;
75 reg = <0x40040080 0x20>;
85 reg = <0x400400a0 0x20>;
95 reg = <0x400400c0 0x20>;
105 reg = <0x400400e0 0x20>;
[all …]
/Zephyr-latest/tests/net/ppp/driver/src/
Dmain.c30 #define NET_LOG_ENABLED 1
45 #define WAIT_TIME_LONG K_SECONDS(1)
50 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
51 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
52 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
66 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
67 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
68 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
73 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
79 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x24, 0x1c, 0x90, 0x7e
[all …]
/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_reg.h18 #define REG_ACCEL_DATA_X0 0x20
71 /* BANK 1 */
148 #define BIT_TEMP_FILT_BW_170 0x20
175 #define SHIFT_INT1_DRIVE_CIRCUIT 1
179 #define BIT_TEMP_DIS 0x20
195 #define BIT_DMP_MEM_RESET_EN 0x20
200 #define BIT_COUNT_BIG_ENDIAN 0x20
224 #define BIT_FIFO_WM_TH 0x20
236 #define BIT_INT_PLL_RDY_INT1_EN 0x20
255 #define BIT_TEST_AZ_EN 0x20
[all …]
/Zephyr-latest/boards/nxp/frdm_rw612/
DW25Q512JVFIQ_FCB.c15 .readSampleClkSrc = 1,
18 .deviceModeCfgEnable = 1,
19 .deviceModeSeq = {.seqNum = 1, .seqId = 2},
34 0x20),
35 [1] = FC_FLEXSPI_LUT_SEQ(
44 [4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ(
69 0x20),
77 0x20),
85 0x20),
86 [4 * 9 + 1] =
/Zephyr-latest/boards/nxp/rd_rw612_bga/
DMX25U51245GZ4I00_FCB.c14 .readSampleClkSrc = 1,
17 .deviceModeCfgEnable = 1,
18 .deviceModeSeq = {.seqNum = 1, .seqId = 2},
33 FC_FLEXSPI_4PAD, 0x20),
34 [1] = FC_FLEXSPI_LUT_SEQ(
41 [4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ(
62 FC_FLEXSPI_1PAD, 0x20),
70 0x20),
78 0x20),
79 [4 * 9 + 1] =
/Zephyr-latest/dts/arm/atmel/
Dsamd21.dtsi14 tcc-1 = &tcc1;
39 reg = <0x42003800 0x20>;
41 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
50 clocks = <&gclk 26>, <&pm 0x20 8>;
62 clocks = <&gclk 26>, <&pm 0x20 9>;
74 clocks = <&gclk 27>, <&pm 0x20 10>;
86 clocks = <&gclk 33>, <&pm 0x20 18>;
92 clocks = <&gclk 0x14>, <&pm 0x20 2>;
98 clocks = <&gclk 0x15>, <&pm 0x20 3>;
104 clocks = <&gclk 0x16>, <&pm 0x20 4>;
[all …]
Dsaml21.dtsi13 tcc-1 = &tcc1;
70 clocks = <&gclk 19>, <&mclk 0x1c 1>;
94 clocks = <&gclk 24>, <&mclk 0x20 1>;
100 clocks = <&gclk 29>, <&mclk 0x20 2>;
107 clocks = <&gclk 30>, <&mclk 0x20 3>;
/Zephyr-latest/dts/arm/renesas/ra/
Dra4-cm4-common.dtsi13 reg = <0x400400c0 0x20>;
22 reg = <0x400400e0 0x20>;
31 reg = <0x40040100 0x20>;
40 reg = <0x40040120 0x20>;
49 reg = <0x40070040 0x20>;
57 #clock-cells = <1>;
Dra-cm4-common.dtsi15 #address-cells = <1>;
122 div = <1>;
153 #address-cells = <1>;
154 #size-cells = <1>;
169 reg = <0x40040000 0x20>;
184 port-irq7-pins = <1 15>;
192 reg = <0x40040020 0x20>;
203 port-irq1-pins = <1>;
213 reg = <0x40040040 0x20>;
232 reg = <0x40040060 0x20>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dra4-cm4-common.dtsi15 #address-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
42 #address-cells = <1>;
43 #size-cells = <1>;
48 reg = <0x40040000 0x20>;
58 reg = <0x40040020 0x20>;
59 port = <1>;
68 reg = <0x40040040 0x20>;
78 reg = <0x40040060 0x20>;
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo3_blue.dtsi20 #address-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <1>;
42 * transition time are both lower than 1us, but considering
53 * the software overhead 1us and deepsleep_to_run transition time
83 #address-cells = <1>;
84 #size-cells = <1>;
108 reg = <0x40008000 0x20>;
117 reg = <0x40008020 0x20>;
126 reg = <0x40008040 0x20>;
[all …]
Dambiq_apollo3p_blue.dtsi20 #address-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <1>;
42 * transition time are both lower than 1us, but considering
53 * is the software overhead 1us and deepsleep_to_run transition
101 #address-cells = <1>;
102 #size-cells = <1>;
126 reg = <0x40008000 0x20>;
135 reg = <0x40008020 0x20>;
144 reg = <0x40008040 0x20>;
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi16 #address-cells = <1>;
52 i2c-smb-1 = &i2c_smb_1;
67 core-clock-div = <1>;
81 #address-cells = <1>;
82 #size-cells = <1>;
88 sources = <0 1 2 4 5 10 16 17>;
94 #address-cells = <1>;
95 #size-cells = <1>;
114 port-id = <1>;
123 interrupts = <1 2>;
[all …]
Dmec5.dtsi15 #address-cells = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
46 interrupts = <0 1>;
51 interrupts = <1 1>;
56 interrupts = <2 1>;
61 interrupts = <3 1>;
66 interrupts = <4 1>;
71 interrupts = <5 1>;
76 interrupts = <6 1>;
[all …]
Dmec172x_common.dtsi15 core-clock-div = <1>;
31 clocks = <&pcr 1 0 MCHP_XEC_PCR_CLK_PERIPH>;
32 #address-cells = <1>;
33 #size-cells = <1>;
42 sources = <0 1 2 3 4 5 6 7
51 interrupts = <1 0>;
52 girq-id = <1>;
53 sources = <0 1 2 3 4 5 6 7
64 sources = <0 1 2 3 4 5 6 7
75 sources = <0 1 2 3 4 5 6 7
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dra6-cm4-common.dtsi16 #address-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <1>;
43 reg = <0x40040000 0x20>;
53 reg = <0x40040020 0x20>;
54 port = <1>;
63 reg = <0x40040040 0x20>;
73 reg = <0x40040060 0x20>;
83 reg = <0x40040080 0x20>;
93 reg = <0x400400a0 0x20>;
[all …]
Dr7fa6m3ax.dtsi13 sram0: memory@1ffe0000 {
20 reg = <0x40040100 0x20>;
30 reg = <0x40040120 0x20>;
40 reg = <0x40040140 0x20>;
50 reg = <0x40040160 0x20>;
60 interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
62 reg = <0x400700a0 0x20>;
74 interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
76 reg = <0x400700c0 0x20>;
88 interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
[all …]
/Zephyr-latest/tests/misc/print_format/
Dtestcase.yaml27 - "x20"
31 - "X20"
41 filter: TOOLCHAIN_HAS_NEWLIB == 1
/Zephyr-latest/tests/kconfig/configdefault/
DKconfig14 bool "SYM Y 1"
20 bool "SYM N 1"
207 default 1
211 int "Int 1"
215 default 1
247 default 0x20
250 hex "Hex 0x20"
257 string "Hex 0x20"
/Zephyr-latest/tests/crypto/tinycrypt/src/
Dhmac.c56 digest, sizeof(digest), 1); in do_hmac_test()
76 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 in ZTEST()
89 result = do_hmac_test(&h, 1, data, sizeof(data), in ZTEST()
105 0x77, 0x68, 0x61, 0x74, 0x20, 0x64, 0x6f, 0x20, 0x79, 0x61, in ZTEST()
106 0x20, 0x77, in ZTEST()
107 0x61, 0x6e, 0x74, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x6e, 0x6f, in ZTEST()
223 0x54, 0x65, 0x73, 0x74, 0x20, 0x57, 0x69, 0x74, 0x68, 0x20, in ZTEST()
232 0x93, 0xf8, 0x60, 0xaa, 0xb0, 0xcd, 0x20, 0xc5 in ZTEST()
275 0x54, 0x65, 0x73, 0x74, 0x20, 0x55, 0x73, 0x69, 0x6e, 0x67, in ZTEST()
276 0x20, 0x4c, in ZTEST()
[all …]
/Zephyr-latest/dts/riscv/ite/
Dit81xx2.dtsi18 reg = <0x00f01d07 1
19 0x00f01d06 1
20 0x00f01d08 1
21 0x00f01d09 1
22 0x00f01d26 1>;
31 reg = <0x00f01d0b 1
32 0x00f01d0a 1
33 0x00f01d01 1
34 0x00f01d0c 1
35 0x00f01d27 1>;
[all …]
/Zephyr-latest/tests/subsys/modem/modem_ppp/src/
Dmain.c43 0x21, 0x7D, 0x20, 0x7D, 0x24, 0xD1, 0xB5, 0x7E};
48 0x7E, 0xFF, 0x7D, 0x23, 0x7D, 0x20, 0x21, 0x45, 0x7D, 0x20, 0x7D, 0x20, 0x29, 0x87, 0x6E,
49 0x40, 0x7D, 0x20, 0xE8, 0x7D, 0x31, 0xC1, 0xE9, 0x7D, 0x23, 0xFB, 0x7D, 0x25, 0x20, 0x7D,
50 0x2A, 0x2B, 0x36, 0x26, 0x25, 0x7D, 0x32, 0x8C, 0x3E, 0x7D, 0x20, 0x7D, 0x35, 0xBD, 0xF3,
51 0x2D, 0x7D, 0x20, 0x7D, 0x2B, 0x7D, 0x20, 0x7D, 0x27, 0x7D, 0x20, 0x7D, 0x24, 0x7D, 0x20,
52 0x7D, 0x24, 0x7D, 0x2A, 0x7D, 0x20, 0x7D, 0x2A, 0x7D, 0x20, 0xD4, 0x31, 0x7E};
56 0x05, 0x20, 0x0A, 0x2B, 0x36, 0x26, 0x25, 0x12, 0x8C, 0x3E, 0x00, 0x15, 0xBD, 0xF3,
61 0xFB, 0x05, 0x20, 0x0A, 0x2B, 0x36, 0x26, 0x25, 0x12, 0x8C, 0x3E, 0x00, 0x15, 0xBD, 0xF3,
66 0x20, 0x7D, 0x24, 0xD1, 0xB5, 0x7E};
153 prng_state = (1103515245 * prng_state + 12345) % (1 << 31); in test_modem_ppp_prng_random()
[all …]
/Zephyr-latest/drivers/memc/
Dmemc_mcux_flexspi_aps6408l.c54 #define APS_6408L_BURST_1K 0x7 /* 1K Hybrid wrap */
61 #define APS_6408L_WLC_200 0x20 /* 200MHz input clock write latency */
86 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x20,
87 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
94 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
101 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
108 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
132 .SeqNumber = 1, in memc_flexspi_aps6408l_get_vendor_id()
135 .dataSize = 1, in memc_flexspi_aps6408l_get_vendor_id()
156 .SeqNumber = 1, in memc_flexspi_aps6408l_update_reg()
[all …]
/Zephyr-latest/tests/drivers/interrupt_controller/intc_plic/src/
Dmain.c19 zassert_equal(1, local_irq_to_reg_index(0x20)); in ZTEST()
20 zassert_equal(1, local_irq_to_reg_index(0x3f)); in ZTEST()
28 zassert_equal(4, local_irq_to_reg_offset(0x20)); in ZTEST()
40 zassert_equal(plic_hart_contexts_0[1], 2); in ZTEST()
50 zassert_equal(plic_hart_contexts_0[1], 1); in ZTEST()

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