1/*
2 * Copyright (c) 2024 TOKITA Hiroshi
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10#include <zephyr/dt-bindings/clock/ra_clock.h>
11#include <zephyr/dt-bindings/pwm/ra_pwm.h>
12#include <freq.h>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu@0 {
20			device_type = "cpu";
21			compatible = "arm,cortex-m23";
22			reg = <0>;
23		};
24	};
25
26	soc {
27		system: system@4001e000 {
28			compatible = "renesas,ra-system";
29			reg = <0x4001e000 0x1000>;
30			status = "okay";
31		};
32
33		ioport0: gpio@40040000 {
34			compatible = "renesas,ra-gpio-ioport";
35			reg = <0x40040000 0x20>;
36			port = <0>;
37			gpio-controller;
38			#gpio-cells = <2>;
39			ngpios = <16>;
40			status = "disabled";
41		};
42
43		ioport1: gpio@40040020 {
44			compatible = "renesas,ra-gpio-ioport";
45			reg = <0x40040020 0x20>;
46			port = <1>;
47			gpio-controller;
48			#gpio-cells = <2>;
49			ngpios = <16>;
50			status = "disabled";
51		};
52
53		ioport2: gpio@40040040 {
54			compatible = "renesas,ra-gpio-ioport";
55			reg = <0x40040040 0x20>;
56			port = <2>;
57			gpio-controller;
58			#gpio-cells = <2>;
59			ngpios = <16>;
60			status = "disabled";
61		};
62
63		ioport3: gpio@40040060 {
64			compatible = "renesas,ra-gpio-ioport";
65			reg = <0x40040060 0x20>;
66			port = <3>;
67			gpio-controller;
68			#gpio-cells = <2>;
69			ngpios = <16>;
70			status = "disabled";
71		};
72
73		ioport4: gpio@40040080 {
74			compatible = "renesas,ra-gpio-ioport";
75			reg = <0x40040080 0x20>;
76			port = <4>;
77			gpio-controller;
78			#gpio-cells = <2>;
79			ngpios = <16>;
80			status = "disabled";
81		};
82
83		ioport5: gpio@400400a0 {
84			compatible = "renesas,ra-gpio-ioport";
85			reg = <0x400400a0 0x20>;
86			port = <5>;
87			gpio-controller;
88			#gpio-cells = <2>;
89			ngpios = <16>;
90			status = "disabled";
91		};
92
93		ioport6: gpio@400400c0 {
94			compatible = "renesas,ra-gpio-ioport";
95			reg = <0x400400c0 0x20>;
96			port = <6>;
97			gpio-controller;
98			#gpio-cells = <2>;
99			ngpios = <16>;
100			status = "disabled";
101		};
102
103		ioport7: gpio@400400e0 {
104			compatible = "renesas,ra-gpio-ioport";
105			reg = <0x400400e0 0x20>;
106			port = <7>;
107			gpio-controller;
108			#gpio-cells = <2>;
109			ngpios = <16>;
110			status = "disabled";
111		};
112
113		ioport8: gpio@40040100 {
114			compatible = "renesas,ra-gpio-ioport";
115			reg = <0x40040100 0x20>;
116			port = <8>;
117			gpio-controller;
118			#gpio-cells = <2>;
119			ngpios = <16>;
120			status = "disabled";
121		};
122
123		ioport9: gpio@40040120 {
124			compatible = "renesas,ra-gpio-ioport";
125			reg = <0x40040120 0x20>;
126			port = <9>;
127			gpio-controller;
128			#gpio-cells = <2>;
129			ngpios = <16>;
130			status = "disabled";
131		};
132
133		pinctrl: pin-controller@40040800 {
134			compatible = "renesas,ra-pinctrl-pfs";
135			reg = <0x40040800 0x3c0>;
136			status = "okay";
137		};
138
139		sci0: sci@40070000 {
140			compatible = "renesas,ra-sci";
141			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
142			interrupt-names = "rxi", "txi", "tei", "eri";
143			reg = <0x40070000 0x20>;
144			clocks = <&pclkb MSTPB 31>;
145			status = "disabled";
146			uart {
147				compatible = "renesas,ra-sci-uart";
148				channel = <0>;
149				status = "disabled";
150			};
151		};
152
153		sci1: sci@40070020 {
154			compatible = "renesas,ra-sci";
155			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
156			interrupt-names = "rxi", "txi", "tei", "eri";
157			reg = <0x40070020 0x20>;
158			clocks = <&pclkb MSTPB 30>;
159			status = "disabled";
160			uart {
161				compatible = "renesas,ra-sci-uart";
162				channel = <1>;
163				status = "disabled";
164			};
165		};
166
167		sci2: sci@40070040 {
168			compatible = "renesas,ra-sci";
169			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
170			interrupt-names = "rxi", "txi", "tei", "eri";
171			reg = <0x40070040 0x20>;
172			clocks = <&pclkb MSTPB 29>;
173			status = "disabled";
174			uart {
175				compatible = "renesas,ra-sci-uart";
176				channel = <2>;
177				status = "disabled";
178			};
179		};
180
181		sci3: sci@40070060 {
182			compatible = "renesas,ra-sci";
183			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
184			interrupt-names = "rxi", "txi", "tei", "eri";
185			reg = <0x40070060 0x20>;
186			clocks = <&pclkb MSTPB 28>;
187			status = "disabled";
188			uart {
189				compatible = "renesas,ra-sci-uart";
190				channel = <3>;
191				status = "disabled";
192			};
193		};
194
195		sci9: sci@40070120 {
196			compatible = "renesas,ra-sci";
197			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
198			interrupt-names = "rxi", "txi", "tei", "eri";
199			reg = <0x40070120 0x20>;
200			clocks = <&pclkb MSTPB 22>;
201			status = "disabled";
202			uart {
203				compatible = "renesas,ra-sci-uart";
204				channel = <9>;
205				status = "disabled";
206			};
207		};
208
209		spi0: spi@40072000 {
210			compatible = "renesas,ra-spi";
211			#address-cells = <1>;
212			#size-cells = <0>;
213			channel = <0>;
214			reg = <0x40072000 0x100>;
215			status = "disabled";
216		};
217
218		spi1: spi@40072100 {
219			compatible = "renesas,ra-spi";
220			#address-cells = <1>;
221			#size-cells = <0>;
222			channel = <1>;
223			interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
224			interrupt-names = "rxi", "txi", "tei", "eri";
225			reg = <0x40072100 0x100>;
226			status = "disabled";
227		};
228
229		iic0: iic0@40053000 {
230			compatible = "renesas,ra-iic";
231			channel = <0>;
232			reg = <0x40053000 0x100>;
233			status = "disabled";
234		};
235
236		iic1: iic1@40053100 {
237			compatible = "renesas,ra-iic";
238			channel = <1>;
239			reg = <0x40053100 0x100>;
240			status = "disabled";
241		};
242
243		flash-controller@407e0000 {
244			reg = <0x407e0000 0x10000>;
245			#address-cells = <1>;
246			#size-cells = <1>;
247		};
248
249		agt0: agt@40084000  {
250			compatible = "renesas,ra-agt";
251			channel = <0>;
252			reg = <0x40084000 0x100>;
253			renesas,count-source = "AGT_CLOCK_LOCO";
254			renesas,prescaler = <0>;
255			renesas,resolution = <16>;
256			status = "disabled";
257
258			counter {
259				compatible = "renesas,ra-agt-counter";
260				status = "disabled";
261			};
262		};
263
264		agt1: agt@40084100 {
265			compatible = "renesas,ra-agt";
266			channel = <1>;
267			reg = <0x40084100 0x100>;
268			renesas,count-source = "AGT_CLOCK_LOCO";
269			renesas,prescaler = <0>;
270			renesas,resolution = <16>;
271			status = "disabled";
272
273			counter {
274				compatible = "renesas,ra-agt-counter";
275				status = "disabled";
276			};
277		};
278
279		id_code: id_code@1010018 {
280			compatible = "zephyr,memory-region";
281			reg = <0x01010018 0x20>;
282			zephyr,memory-region = "ID_CODE";
283			status = "okay";
284		};
285
286		port_irq0: external-interrupt@40006000 {
287			compatible = "renesas,ra-external-interrupt";
288			reg = <0x40006000 0x1>;
289			channel = <0>;
290			renesas,sample-clock-div = <64>;
291			#port-irq-cells = <0>;
292			status = "disabled";
293		};
294
295		port_irq1: external-interrupt@40006001 {
296			compatible = "renesas,ra-external-interrupt";
297			reg = <0x40006001 0x1>;
298			channel = <1>;
299			renesas,sample-clock-div = <64>;
300			#port-irq-cells = <0>;
301			status = "disabled";
302		};
303
304		port_irq2: external-interrupt@40006002 {
305			compatible = "renesas,ra-external-interrupt";
306			reg = <0x40006002 0x1>;
307			channel = <2>;
308			renesas,sample-clock-div = <64>;
309			#port-irq-cells = <0>;
310			status = "disabled";
311		};
312
313		port_irq3: external-interrupt@40006003 {
314			compatible = "renesas,ra-external-interrupt";
315			reg = <0x40006003 0x1>;
316			channel = <3>;
317			renesas,sample-clock-div = <64>;
318			#port-irq-cells = <0>;
319			status = "disabled";
320		};
321
322		port_irq4: external-interrupt@40006004 {
323			compatible = "renesas,ra-external-interrupt";
324			reg = <0x40006004 0x1>;
325			channel = <4>;
326			renesas,sample-clock-div = <64>;
327			#port-irq-cells = <0>;
328			status = "disabled";
329		};
330
331		port_irq5: external-interrupt@40006005 {
332			compatible = "renesas,ra-external-interrupt";
333			reg = <0x40006005 0x1>;
334			channel = <5>;
335			renesas,sample-clock-div = <64>;
336			#port-irq-cells = <0>;
337			status = "disabled";
338		};
339
340		port_irq6: external-interrupt@40006006 {
341			compatible = "renesas,ra-external-interrupt";
342			reg = <0x40006006 0x1>;
343			channel = <6>;
344			renesas,sample-clock-div = <64>;
345			#port-irq-cells = <0>;
346			status = "disabled";
347		};
348
349		port_irq7: external-interrupt@40006007 {
350			compatible = "renesas,ra-external-interrupt";
351			reg = <0x40006007 0x1>;
352			channel = <7>;
353			renesas,sample-clock-div = <64>;
354			#port-irq-cells = <0>;
355			status = "disabled";
356		};
357
358		pwm0: pwm0@40078000 {
359			compatible = "renesas,ra-pwm";
360			divider = <RA_PWM_SOURCE_DIV_1>;
361			channel = <RA_PWM_CHANNEL_0>;
362			clocks = <&pclkd MSTPD 5>;
363			reg = <0x40078000 0x100>;
364			#pwm-cells = <3>;
365			status = "disabled";
366		};
367	};
368};
369
370&nvic {
371	arm,num-irq-priority-bits = <2>;
372};
373