Lines Matching +full:1 +full:x20
18 #define REG_ACCEL_DATA_X0 0x20
71 /* BANK 1 */
148 #define BIT_TEMP_FILT_BW_170 0x20
175 #define SHIFT_INT1_DRIVE_CIRCUIT 1
179 #define BIT_TEMP_DIS 0x20
195 #define BIT_DMP_MEM_RESET_EN 0x20
200 #define BIT_COUNT_BIG_ENDIAN 0x20
224 #define BIT_FIFO_WM_TH 0x20
236 #define BIT_INT_PLL_RDY_INT1_EN 0x20
255 #define BIT_TEST_AZ_EN 0x20
268 #define BIT_INT_STATUS_PLL_DRY 0x20
285 #define BIT_INT_STATUS_STEP_DET 0x20
296 #define BIT_ACCEL_UI_LNM_BW_5_IIR 0x20
305 #define BIT_ACCEL_UI_LPM_AVG_2 0x20
345 #define BIT_EN_DREG_FIFO_D2A 0x20
358 #define BIT_PEDO_ENABLE 0x20
413 #define BIT_INT_STEP_DET_INT1_EN 0x20
422 #define BIT_INT_STEP_DET_INT2_EN 0x20
431 #define BIT_INT_FSYNC_IBI_EN 0x20
447 #define BIT_INT_STEP_DET_IBI_EN 0x20
452 #define BIT_FIFO_HEAD_GYRO 0x20
471 /* scale by 100, 1LSB=1degC, 9447 */
493 #define BYTES_FOR_TEMP 1
516 * Polarity: 0 -> Active Low, 1 -> Active High
517 * Drive circuit: 0 -> Open Drain, 1 -> Push-Pull
518 * Mode: 0 -> Pulse, 1 -> Latch
520 #define INT_POLARITY 1
521 #define INT_DRIVE_CIRCUIT 1