1 /*
2  * Copyright 2021-2023 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 #include <flash_config.h>
8 
9 __attribute__((section(".flash_conf"), used))
10 const fc_flexspi_nor_config_t flexspi_config = {
11 	.memConfig = {
12 			.tag = FC_BLOCK_TAG,
13 			.version = FC_BLOCK_VERSION,
14 			.readSampleClkSrc = 1,
15 			.csHoldTime = 3,
16 			.csSetupTime = 3,
17 			.deviceModeCfgEnable = 1,
18 			.deviceModeSeq = {.seqNum = 1, .seqId = 2},
19 			.deviceModeArg = 0xC740,
20 			.configCmdEnable = 0,
21 			.deviceType = 0x1,
22 			.sflashPadType = kSerialFlash_4Pads,
23 			.serialClkFreq = 7,
24 			.sflashA1Size = 0x4000000U,
25 			.sflashA2Size = 0,
26 			.sflashB1Size = 0,
27 			.sflashB2Size = 0,
28 			.lookupTable = {
29 					/* Read */
30 					[0] = FC_FLEXSPI_LUT_SEQ(
31 						FC_CMD_SDR, FC_FLEXSPI_1PAD,
32 						0xEC, FC_RADDR_SDR,
33 						FC_FLEXSPI_4PAD, 0x20),
34 					[1] = FC_FLEXSPI_LUT_SEQ(
35 						FC_DUMMY_SDR,
36 						FC_FLEXSPI_4PAD, 0x0A,
37 						FC_READ_SDR,
38 						FC_FLEXSPI_4PAD, 0x04),
39 
40 					/* Read Status */
41 					[4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ(
42 						FC_CMD_SDR, FC_FLEXSPI_1PAD,
43 						0x05, FC_READ_SDR,
44 						FC_FLEXSPI_1PAD, 0x04),
45 
46 					/* Write Status */
47 					[4 * 2 + 0] = FC_FLEXSPI_LUT_SEQ(
48 						FC_CMD_SDR, FC_FLEXSPI_1PAD,
49 						0x01, FC_WRITE_SDR,
50 						FC_FLEXSPI_1PAD, 0x02),
51 
52 					/* Write Enable */
53 					[4 * 3 + 0] = FC_FLEXSPI_LUT_SEQ(
54 						FC_CMD_SDR, FC_FLEXSPI_1PAD,
55 						0x06, FC_STOP_EXE,
56 						FC_FLEXSPI_1PAD, 0x00),
57 
58 					/* Sector erase */
59 					[4 * 5 + 0] = FC_FLEXSPI_LUT_SEQ(
60 						FC_CMD_SDR, FC_FLEXSPI_1PAD,
61 						0x21, FC_RADDR_SDR,
62 						FC_FLEXSPI_1PAD, 0x20),
63 
64 					/* Block erase */
65 					[4 * 8 + 0] =
66 						FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR,
67 								   FC_FLEXSPI_1PAD,
68 								   0x5C, FC_RADDR_SDR,
69 								   FC_FLEXSPI_1PAD,
70 								   0x20),
71 
72 					/* Page program */
73 					[4 * 9 + 0] =
74 						FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR,
75 								   FC_FLEXSPI_1PAD,
76 								   0x12, FC_RADDR_SDR,
77 								   FC_FLEXSPI_1PAD,
78 								   0x20),
79 					[4 * 9 + 1] =
80 						FC_FLEXSPI_LUT_SEQ(FC_WRITE_SDR,
81 								   FC_FLEXSPI_1PAD,
82 								   0x00,
83 								   FC_STOP_EXE, FC_FLEXSPI_1PAD,
84 								   0x00),
85 
86 					/* chip erase */
87 					[4 * 11 + 0] = FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR,
88 									  FC_FLEXSPI_1PAD,
89 									  0x60, FC_STOP_EXE,
90 									  FC_FLEXSPI_1PAD,
91 									  0x00),
92 				},
93 	},
94 	.pageSize = 0x100,
95 	.sectorSize = 0x1000,
96 	.ipcmdSerialClkFreq = 0,
97 	.blockSize = 0x8000,
98 	.fcb_fill[0] = 0xFFFFFFFF,
99 };
100