1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10#include <zephyr/dt-bindings/pwm/ra_pwm.h>
11#include <freq.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-m4";
21			reg = <0>;
22			#address-cells = <1>;
23			#size-cells = <1>;
24
25			mpu: mpu@e000ed90 {
26				compatible = "arm,armv7m-mpu";
27				reg = <0xe000ed90 0x40>;
28			};
29
30		};
31	};
32
33	soc {
34		system: system@4001e000 {
35			compatible = "renesas,ra-system";
36			reg = <0x4001e000 0x1000>;
37			status = "okay";
38		};
39
40		flash-controller@407e0000 {
41			reg = <0x407e0000 0x10000>;
42			#address-cells = <1>;
43			#size-cells = <1>;
44		};
45
46		ioport0: gpio@40040000 {
47			compatible = "renesas,ra-gpio-ioport";
48			reg = <0x40040000 0x20>;
49			port = <0>;
50			gpio-controller;
51			#gpio-cells = <2>;
52			ngpios = <16>;
53			status = "disabled";
54		};
55
56		ioport1: gpio@40040020 {
57			compatible = "renesas,ra-gpio-ioport";
58			reg = <0x40040020 0x20>;
59			port = <1>;
60			gpio-controller;
61			#gpio-cells = <2>;
62			ngpios = <16>;
63			status = "disabled";
64		};
65
66		ioport2: gpio@40040040 {
67			compatible = "renesas,ra-gpio-ioport";
68			reg = <0x40040040 0x20>;
69			port = <2>;
70			gpio-controller;
71			#gpio-cells = <2>;
72			ngpios = <16>;
73			status = "disabled";
74		};
75
76		ioport3: gpio@40040060 {
77			compatible = "renesas,ra-gpio-ioport";
78			reg = <0x40040060 0x20>;
79			port = <3>;
80			gpio-controller;
81			#gpio-cells = <2>;
82			ngpios = <16>;
83			status = "disabled";
84		};
85
86		ioport4: gpio@40040080 {
87			compatible = "renesas,ra-gpio-ioport";
88			reg = <0x40040080 0x20>;
89			port = <4>;
90			gpio-controller;
91			#gpio-cells = <2>;
92			ngpios = <16>;
93			status = "disabled";
94		};
95
96		ioport5: gpio@400400a0 {
97			compatible = "renesas,ra-gpio-ioport";
98			reg = <0x400400a0 0x20>;
99			port = <5>;
100			gpio-controller;
101			#gpio-cells = <2>;
102			ngpios = <16>;
103			status = "disabled";
104		};
105
106		ioport9: gpio@40040120 {
107			compatible = "renesas,ra-gpio-ioport";
108			reg = <0x40040120 0x20>;
109			port = <9>;
110			gpio-controller;
111			#gpio-cells = <2>;
112			ngpios = <16>;
113			status = "disabled";
114		};
115
116		pinctrl: pin-controller@40040800 {
117			compatible = "renesas,ra-pinctrl-pfs";
118			reg = <0x40040800 0x3c0>;
119			status = "okay";
120		};
121
122		sci0: sci0@40070000  {
123			compatible = "renesas,ra-sci";
124			interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
125			interrupt-names = "rxi", "txi", "tei", "eri";
126			reg = <0x40070000 0x20>;
127			clocks = <&pclka MSTPB 31>;
128			status = "disabled";
129			uart {
130				compatible = "renesas,ra-sci-uart";
131				channel = <0>;
132				status = "disabled";
133			};
134		};
135
136		sci1: sci1@40070020  {
137			compatible = "renesas,ra-sci";
138			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
139			interrupt-names = "rxi", "txi", "tei", "eri";
140			reg = <0x40070020 0x20>;
141			clocks = <&pclka MSTPB 30>;
142			status = "disabled";
143			uart {
144				compatible = "renesas,ra-sci-uart";
145				channel = <1>;
146				status = "disabled";
147			};
148		};
149
150		sci9: sci9@40070120  {
151			compatible = "renesas,ra-sci";
152			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
153			interrupt-names = "rxi", "txi", "tei", "eri";
154			reg = <0x40070120 0x20>;
155			clocks = <&pclka MSTPB 22>;
156			status = "disabled";
157			uart {
158				compatible = "renesas,ra-sci-uart";
159				channel = <9>;
160				status = "disabled";
161			};
162		};
163
164		spi0: spi@40072000 {
165			compatible = "renesas,ra-spi";
166			#address-cells = <1>;
167			#size-cells = <0>;
168			channel = <0>;
169			reg = <0x40072000 0x100>;
170			status = "disabled";
171		};
172
173		spi1: spi@40072100 {
174			compatible = "renesas,ra-spi";
175			#address-cells = <1>;
176			#size-cells = <0>;
177			channel = <1>;
178			interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
179			interrupt-names = "rxi", "txi", "tei", "eri";
180			reg = <0x40072100 0x100>;
181			status = "disabled";
182		};
183
184		agt0: agt@40084000  {
185			compatible = "renesas,ra-agt";
186			channel = <0>;
187			reg = <0x40084000 0x100>;
188			renesas,count-source = "AGT_CLOCK_LOCO";
189			renesas,prescaler = <0>;
190			renesas,resolution = <16>;
191			status = "disabled";
192
193			counter {
194				compatible = "renesas,ra-agt-counter";
195				status = "disabled";
196			};
197		};
198
199		agt1: agt@40084100 {
200			compatible = "renesas,ra-agt";
201			channel = <1>;
202			reg = <0x40084100 0x100>;
203			renesas,count-source = "AGT_CLOCK_LOCO";
204			renesas,prescaler = <0>;
205			renesas,resolution = <16>;
206			status = "disabled";
207
208			counter {
209				compatible = "renesas,ra-agt-counter";
210				status = "disabled";
211			};
212		};
213
214		adc0: adc@4005c000 {
215			compatible = "renesas,ra-adc";
216			interrupt-names = "scanend";
217			reg = <0x4005c000 0x100>;
218			#io-channel-cells = <1>;
219			vref-mv = <3300>;
220			status = "disabled";
221		};
222
223		adc1: adc@4005c200 {
224			compatible = "renesas,ra-adc";
225			interrupt-names = "scanend";
226			reg = <0x4005c200 0x100>;
227			#io-channel-cells = <1>;
228			vref-mv = <3300>;
229			status = "disabled";
230		};
231
232		iic0: iic0@40053000 {
233			compatible = "renesas,ra-iic";
234			channel = <0>;
235			reg = <0x40053000 0x100>;
236			status = "disabled";
237		};
238
239		iic1: iic1@40053100 {
240			compatible = "renesas,ra-iic";
241			channel = <1>;
242			reg = <0x40053100 0x100>;
243			status = "disabled";
244		};
245
246		id_code: id_code@1010018 {
247			compatible = "zephyr,memory-region";
248			reg = <0x01010018 0x20>;
249			zephyr,memory-region = "ID_CODE";
250			status = "okay";
251		};
252
253		port_irq0: external-interrupt@40006000 {
254			compatible = "renesas,ra-external-interrupt";
255			reg = <0x40006000 0x1>;
256			channel = <0>;
257			renesas,sample-clock-div = <64>;
258			#port-irq-cells = <0>;
259			status = "disabled";
260		};
261
262		port_irq1: external-interrupt@40006001 {
263			compatible = "renesas,ra-external-interrupt";
264			reg = <0x40006001 0x1>;
265			channel = <1>;
266			renesas,sample-clock-div = <64>;
267			#port-irq-cells = <0>;
268			status = "disabled";
269		};
270
271		port_irq2: external-interrupt@40006002 {
272			compatible = "renesas,ra-external-interrupt";
273			reg = <0x40006002 0x1>;
274			channel = <2>;
275			renesas,sample-clock-div = <64>;
276			#port-irq-cells = <0>;
277			status = "disabled";
278		};
279
280		port_irq3: external-interrupt@40006003 {
281			compatible = "renesas,ra-external-interrupt";
282			reg = <0x40006003 0x1>;
283			channel = <3>;
284			renesas,sample-clock-div = <64>;
285			#port-irq-cells = <0>;
286			status = "disabled";
287		};
288
289		port_irq4: external-interrupt@40006004 {
290			compatible = "renesas,ra-external-interrupt";
291			reg = <0x40006004 0x1>;
292			channel = <4>;
293			renesas,sample-clock-div = <64>;
294			#port-irq-cells = <0>;
295			status = "disabled";
296		};
297
298		port_irq6: external-interrupt@40006006 {
299			compatible = "renesas,ra-external-interrupt";
300			reg = <0x40006006 0x1>;
301			channel = <6>;
302			renesas,sample-clock-div = <64>;
303			#port-irq-cells = <0>;
304			status = "disabled";
305		};
306
307		port_irq7: external-interrupt@40006007 {
308			compatible = "renesas,ra-external-interrupt";
309			reg = <0x40006007 0x1>;
310			channel = <7>;
311			renesas,sample-clock-div = <64>;
312			#port-irq-cells = <0>;
313			status = "disabled";
314		};
315
316		port_irq9: external-interrupt@40006009 {
317			compatible = "renesas,ra-external-interrupt";
318			reg = <0x40006009 0x1>;
319			channel = <9>;
320			renesas,sample-clock-div = <64>;
321			#port-irq-cells = <0>;
322			status = "disabled";
323		};
324
325		port_irq11: external-interrupt@4000600b {
326			compatible = "renesas,ra-external-interrupt";
327			reg = <0x4000600b 0x1>;
328			channel = <11>;
329			renesas,sample-clock-div = <64>;
330			#port-irq-cells = <0>;
331			status = "disabled";
332		};
333
334		port_irq14: external-interrupt@4000600e {
335			compatible = "renesas,ra-external-interrupt";
336			reg = <0x4000600e 0x1>;
337			channel = <14>;
338			renesas,sample-clock-div = <64>;
339			#port-irq-cells = <0>;
340			status = "disabled";
341		};
342
343		port_irq15: external-interrupt@4000600f {
344			compatible = "renesas,ra-external-interrupt";
345			reg = <0x4000600f 0x1>;
346			channel = <15>;
347			renesas,sample-clock-div = <64>;
348			#port-irq-cells = <0>;
349			status = "disabled";
350		};
351
352		pwm0: pwm0@40169000 {
353			compatible = "renesas,ra-pwm";
354			divider = <RA_PWM_SOURCE_DIV_1>;
355			channel = <RA_PWM_CHANNEL_0>;
356			clocks = <&pclkd MSTPD 5>;
357			reg = <0x40169000 0x100>;
358			#pwm-cells = <3>;
359			status = "disabled";
360		};
361
362		pwm1: pwm1@40169100 {
363			compatible = "renesas,ra-pwm";
364			divider = <RA_PWM_SOURCE_DIV_1>;
365			channel = <RA_PWM_CHANNEL_1>;
366			clocks = <&pclkd MSTPD 5>;
367			reg = <0x40169100 0x100>;
368			#pwm-cells = <3>;
369			status = "disabled";
370		};
371
372		pwm2: pwm2@40169200 {
373			compatible = "renesas,ra-pwm";
374			divider = <RA_PWM_SOURCE_DIV_1>;
375			channel = <RA_PWM_CHANNEL_2>;
376			clocks = <&pclkd MSTPD 5>;
377			reg = <0x40169200 0x100>;
378			#pwm-cells = <3>;
379			status = "disabled";
380		};
381
382		pwm3: pwm3@40169300 {
383			compatible = "renesas,ra-pwm";
384			divider = <RA_PWM_SOURCE_DIV_1>;
385			channel = <RA_PWM_CHANNEL_3>;
386			clocks = <&pclkd MSTPD 5>;
387			reg = <0x40169300 0x100>;
388			#pwm-cells = <3>;
389			status = "disabled";
390		};
391
392		pwm4: pwm4@40169400 {
393			compatible = "renesas,ra-pwm";
394			divider = <RA_PWM_SOURCE_DIV_1>;
395			channel = <RA_PWM_CHANNEL_4>;
396			clocks = <&pclkd MSTPD 5>;
397			reg = <0x40169400 0x100>;
398			#pwm-cells = <3>;
399			status = "disabled";
400		};
401
402		pwm5: pwm5@40169500 {
403			compatible = "renesas,ra-pwm";
404			divider = <RA_PWM_SOURCE_DIV_1>;
405			channel = <RA_PWM_CHANNEL_5>;
406			clocks = <&pclkd MSTPD 6>;
407			reg = <0x40169500 0x100>;
408			#pwm-cells = <3>;
409			status = "disabled";
410		};
411	};
412};
413
414&nvic {
415	arm,num-irq-priority-bits = <4>;
416};
417