1/* 2 * Copyright (c) 2024 Renesas Electronics Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv7-m.dtsi> 9#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h> 10#include <zephyr/dt-bindings/clock/ra_clock.h> 11#include <zephyr/dt-bindings/pwm/ra_pwm.h> 12#include <freq.h> 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-m4"; 22 reg = <0>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 mpu: mpu@e000ed90 { 27 compatible = "arm,armv7m-mpu"; 28 reg = <0xe000ed90 0x40>; 29 }; 30 }; 31 }; 32 33 soc { 34 35 system: system@4001e000 { 36 compatible = "renesas,ra-system"; 37 reg = <0x4001e000 0x1000>; 38 status = "okay"; 39 }; 40 41 ioport0: gpio@40040000 { 42 compatible = "renesas,ra-gpio-ioport"; 43 reg = <0x40040000 0x20>; 44 port = <0>; 45 gpio-controller; 46 #gpio-cells = <2>; 47 ngpios = <16>; 48 status = "disabled"; 49 }; 50 51 ioport1: gpio@40040020 { 52 compatible = "renesas,ra-gpio-ioport"; 53 reg = <0x40040020 0x20>; 54 port = <1>; 55 gpio-controller; 56 #gpio-cells = <2>; 57 ngpios = <16>; 58 status = "disabled"; 59 }; 60 61 ioport2: gpio@40040040 { 62 compatible = "renesas,ra-gpio-ioport"; 63 reg = <0x40040040 0x20>; 64 port = <2>; 65 gpio-controller; 66 #gpio-cells = <2>; 67 ngpios = <16>; 68 status = "disabled"; 69 }; 70 71 ioport3: gpio@40040060 { 72 compatible = "renesas,ra-gpio-ioport"; 73 reg = <0x40040060 0x20>; 74 port = <3>; 75 gpio-controller; 76 #gpio-cells = <2>; 77 ngpios = <16>; 78 status = "disabled"; 79 }; 80 81 ioport4: gpio@40040080 { 82 compatible = "renesas,ra-gpio-ioport"; 83 reg = <0x40040080 0x20>; 84 port = <4>; 85 gpio-controller; 86 #gpio-cells = <2>; 87 ngpios = <16>; 88 status = "disabled"; 89 }; 90 91 ioport5: gpio@400400a0 { 92 compatible = "renesas,ra-gpio-ioport"; 93 reg = <0x400400a0 0x20>; 94 port = <5>; 95 gpio-controller; 96 #gpio-cells = <2>; 97 ngpios = <16>; 98 status = "disabled"; 99 }; 100 101 ioport6: gpio@400400c0 { 102 compatible = "renesas,ra-gpio-ioport"; 103 reg = <0x400400c0 0x20>; 104 port = <6>; 105 gpio-controller; 106 #gpio-cells = <2>; 107 ngpios = <16>; 108 status = "disabled"; 109 }; 110 111 ioport7: gpio@400400e0 { 112 compatible = "renesas,ra-gpio-ioport"; 113 reg = <0x400400e0 0x20>; 114 port = <7>; 115 gpio-controller; 116 #gpio-cells = <2>; 117 ngpios = <16>; 118 status = "disabled"; 119 }; 120 121 pinctrl: pin-contrller@40040800 { 122 compatible = "renesas,ra-pinctrl-pfs"; 123 reg = <0x40040800 0x3c0>; 124 status = "okay"; 125 }; 126 127 sci0: sci0@40070000 { 128 compatible = "renesas,ra-sci"; 129 interrupts = <0 1>, <1 1>, <2 1>, <3 1>; 130 interrupt-names = "rxi", "txi", "tei", "eri"; 131 reg = <0x40070000 0x20>; 132 clocks = <&pclka MSTPB 31>; 133 status = "disabled"; 134 uart { 135 compatible = "renesas,ra-sci-uart"; 136 channel = <0>; 137 status = "disabled"; 138 }; 139 }; 140 141 sci1: sci1@40070020 { 142 compatible = "renesas,ra-sci"; 143 interrupts = <4 1>, <5 1>, <6 1>, <7 1>; 144 interrupt-names = "rxi", "txi", "tei", "eri"; 145 reg = <0x40070020 0x20>; 146 clocks = <&pclka MSTPB 30>; 147 status = "disabled"; 148 uart { 149 compatible = "renesas,ra-sci-uart"; 150 channel = <1>; 151 status = "disabled"; 152 }; 153 }; 154 155 sci2: sci2@40070040 { 156 compatible = "renesas,ra-sci"; 157 interrupts = <8 1>, <9 1>, <10 1>, <11 1>; 158 interrupt-names = "rxi", "txi", "tei", "eri"; 159 reg = <0x40070040 0x20>; 160 clocks = <&pclka MSTPB 29>; 161 status = "disabled"; 162 uart { 163 compatible = "renesas,ra-sci-uart"; 164 channel = <2>; 165 status = "disabled"; 166 }; 167 }; 168 169 sci3: sci3@40070060 { 170 compatible = "renesas,ra-sci"; 171 interrupts = <12 1>, <13 1>, <14 1>, <15 1>; 172 interrupt-names = "rxi", "txi", "tei", "eri"; 173 reg = <0x40070060 0x20>; 174 clocks = <&pclka MSTPB 27>; 175 status = "disabled"; 176 uart { 177 compatible = "renesas,ra-sci-uart"; 178 channel = <3>; 179 status = "disabled"; 180 }; 181 }; 182 183 sci4: sci4@40070080 { 184 compatible = "renesas,ra-sci"; 185 interrupts = <16 1>, <17 1>, <18 1>, <19 1>; 186 interrupt-names = "rxi", "txi", "tei", "eri"; 187 reg = <0x40070080 0x20>; 188 clocks = <&pclka MSTPB 26>; 189 status = "disabled"; 190 uart { 191 compatible = "renesas,ra-sci-uart"; 192 channel = <4>; 193 status = "disabled"; 194 }; 195 }; 196 197 sci8: sci8@40070100 { 198 compatible = "renesas,ra-sci"; 199 interrupts = <32 1>, <33 1>, <34 1>, <35 1>; 200 interrupt-names = "rxi", "txi", "tei", "eri"; 201 reg = <0x40070100 0x20>; 202 clocks = <&pclka MSTPB 23>; 203 status = "disabled"; 204 uart { 205 compatible = "renesas,ra-sci-uart"; 206 channel = <8>; 207 status = "disabled"; 208 }; 209 }; 210 211 sci9: sci9@40070120 { 212 compatible = "renesas,ra-sci"; 213 interrupts = <36 1>, <37 1>, <38 1>, <39 1>; 214 interrupt-names = "rxi", "txi", "tei", "eri"; 215 reg = <0x40070120 0x20>; 216 clocks = <&pclka MSTPB 22>; 217 status = "disabled"; 218 uart { 219 compatible = "renesas,ra-sci-uart"; 220 channel = <9>; 221 status = "disabled"; 222 }; 223 }; 224 225 iic0: iic0@40053000 { 226 compatible = "renesas,ra-iic"; 227 channel = <0>; 228 reg = <0x40053000 0x100>; 229 status = "disabled"; 230 }; 231 232 iic1: iic1@40053100 { 233 compatible = "renesas,ra-iic"; 234 channel = <1>; 235 reg = <0x40053100 0x100>; 236 status = "disabled"; 237 }; 238 239 spi0: spi@40072000 { 240 compatible = "renesas,ra-spi"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 channel = <0>; 244 interrupts = <40 1>, <41 1>, <42 1>, <43 1>; 245 interrupt-names = "rxi", "txi", "tei", "eri"; 246 reg = <0x40072000 0x100>; 247 status = "disabled"; 248 }; 249 250 spi1: spi@40072100 { 251 compatible = "renesas,ra-spi"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 channel = <1>; 255 interrupts = <44 1>, <45 1>, <46 1>, <47 1>; 256 interrupt-names = "rxi", "txi", "tei", "eri"; 257 reg = <0x40072100 0x100>; 258 status = "disabled"; 259 }; 260 261 agt0: agt@40084000 { 262 compatible = "renesas,ra-agt"; 263 channel = <0>; 264 reg = <0x40084000 0x100>; 265 renesas,count-source = "AGT_CLOCK_LOCO"; 266 renesas,prescaler = <0>; 267 renesas,resolution = <16>; 268 status = "disabled"; 269 270 counter { 271 compatible = "renesas,ra-agt-counter"; 272 status = "disabled"; 273 }; 274 }; 275 276 agt1: agt@40084100 { 277 compatible = "renesas,ra-agt"; 278 channel = <1>; 279 reg = <0x40084100 0x100>; 280 renesas,count-source = "AGT_CLOCK_LOCO"; 281 renesas,prescaler = <0>; 282 renesas,resolution = <16>; 283 status = "disabled"; 284 285 counter { 286 compatible = "renesas,ra-agt-counter"; 287 status = "disabled"; 288 }; 289 }; 290 291 adc0: adc@4005c000 { 292 compatible = "renesas,ra-adc"; 293 interrupts = <40 1>; 294 interrupt-names = "scanend"; 295 reg = <0x4005c000 0x100>; 296 #io-channel-cells = <1>; 297 vref-mv = <3300>; 298 status = "disabled"; 299 }; 300 301 adc1: adc@4005c200 { 302 compatible = "renesas,ra-adc"; 303 interrupts = <41 1>; 304 interrupt-names = "scanend"; 305 reg = <0x4005c200 0x100>; 306 #io-channel-cells = <1>; 307 vref-mv = <3300>; 308 status = "disabled"; 309 }; 310 311 id_code: id_code@100a150 { 312 compatible = "zephyr,memory-region"; 313 reg = <0x0100a150 0x10>; 314 zephyr,memory-region = "ID_CODE"; 315 status = "okay"; 316 }; 317 318 port_irq0: external-interrupt@40006000 { 319 compatible = "renesas,ra-external-interrupt"; 320 reg = <0x40006000 0x1>; 321 channel = <0>; 322 renesas,sample-clock-div = <64>; 323 #port-irq-cells = <0>; 324 status = "disabled"; 325 }; 326 327 port_irq1: external-interrupt@40006001 { 328 compatible = "renesas,ra-external-interrupt"; 329 reg = <0x40006001 0x1>; 330 channel = <1>; 331 renesas,sample-clock-div = <64>; 332 #port-irq-cells = <0>; 333 status = "disabled"; 334 }; 335 336 port_irq2: external-interrupt@40006002 { 337 compatible = "renesas,ra-external-interrupt"; 338 reg = <0x40006002 0x1>; 339 channel = <2>; 340 renesas,sample-clock-div = <64>; 341 #port-irq-cells = <0>; 342 status = "disabled"; 343 }; 344 345 port_irq3: external-interrupt@40006003 { 346 compatible = "renesas,ra-external-interrupt"; 347 reg = <0x40006003 0x1>; 348 channel = <3>; 349 renesas,sample-clock-div = <64>; 350 #port-irq-cells = <0>; 351 status = "disabled"; 352 }; 353 354 port_irq4: external-interrupt@40006004 { 355 compatible = "renesas,ra-external-interrupt"; 356 reg = <0x40006004 0x1>; 357 channel = <4>; 358 renesas,sample-clock-div = <64>; 359 #port-irq-cells = <0>; 360 status = "disabled"; 361 }; 362 363 port_irq5: external-interrupt@40006005 { 364 compatible = "renesas,ra-external-interrupt"; 365 reg = <0x40006005 0x1>; 366 channel = <5>; 367 renesas,sample-clock-div = <64>; 368 #port-irq-cells = <0>; 369 status = "disabled"; 370 }; 371 372 port_irq6: external-interrupt@40006006 { 373 compatible = "renesas,ra-external-interrupt"; 374 reg = <0x40006006 0x1>; 375 channel = <6>; 376 renesas,sample-clock-div = <64>; 377 #port-irq-cells = <0>; 378 status = "disabled"; 379 }; 380 381 port_irq7: external-interrupt@40006007 { 382 compatible = "renesas,ra-external-interrupt"; 383 reg = <0x40006007 0x1>; 384 channel = <7>; 385 renesas,sample-clock-div = <64>; 386 #port-irq-cells = <0>; 387 status = "disabled"; 388 }; 389 390 port_irq8: external-interrupt@40006008 { 391 compatible = "renesas,ra-external-interrupt"; 392 reg = <0x40006008 0x1>; 393 channel = <8>; 394 renesas,sample-clock-div = <64>; 395 #port-irq-cells = <0>; 396 status = "disabled"; 397 }; 398 399 port_irq9: external-interrupt@40006009 { 400 compatible = "renesas,ra-external-interrupt"; 401 reg = <0x40006009 0x1>; 402 channel = <9>; 403 renesas,sample-clock-div = <64>; 404 #port-irq-cells = <0>; 405 status = "disabled"; 406 }; 407 408 port_irq10: external-interrupt@4000600a { 409 compatible = "renesas,ra-external-interrupt"; 410 reg = <0x4000600a 0x1>; 411 channel = <10>; 412 renesas,sample-clock-div = <64>; 413 #port-irq-cells = <0>; 414 status = "disabled"; 415 }; 416 417 port_irq11: external-interrupt@4000600b { 418 compatible = "renesas,ra-external-interrupt"; 419 reg = <0x4000600b 0x1>; 420 channel = <11>; 421 renesas,sample-clock-div = <64>; 422 #port-irq-cells = <0>; 423 status = "disabled"; 424 }; 425 426 port_irq12: external-interrupt@4000600c { 427 compatible = "renesas,ra-external-interrupt"; 428 reg = <0x4000600c 0x1>; 429 channel = <12>; 430 renesas,sample-clock-div = <64>; 431 #port-irq-cells = <0>; 432 status = "disabled"; 433 }; 434 435 port_irq13: external-interrupt@4000600d { 436 compatible = "renesas,ra-external-interrupt"; 437 reg = <0x4000600d 0x1>; 438 channel = <13>; 439 renesas,sample-clock-div = <64>; 440 #port-irq-cells = <0>; 441 status = "disabled"; 442 }; 443 444 port_irq14: external-interrupt@4000600e { 445 compatible = "renesas,ra-external-interrupt"; 446 reg = <0x4000600e 0x1>; 447 channel = <14>; 448 renesas,sample-clock-div = <64>; 449 #port-irq-cells = <0>; 450 status = "disabled"; 451 }; 452 453 port_irq15: external-interrupt@4000600f { 454 compatible = "renesas,ra-external-interrupt"; 455 reg = <0x4000600f 0x1>; 456 channel = <15>; 457 renesas,sample-clock-div = <64>; 458 #port-irq-cells = <0>; 459 status = "disabled"; 460 }; 461 462 pwm0: pwm0@40078000 { 463 compatible = "renesas,ra-pwm"; 464 divider = <RA_PWM_SOURCE_DIV_1>; 465 channel = <RA_PWM_CHANNEL_0>; 466 clocks = <&pclkd MSTPD 5>; 467 reg = <0x40078000 0x100>; 468 #pwm-cells = <3>; 469 status = "disabled"; 470 }; 471 472 pwm1: pwm1@40078100 { 473 compatible = "renesas,ra-pwm"; 474 divider = <RA_PWM_SOURCE_DIV_1>; 475 channel = <RA_PWM_CHANNEL_1>; 476 clocks = <&pclkd MSTPD 5>; 477 reg = <0x40078100 0x100>; 478 #pwm-cells = <3>; 479 status = "disabled"; 480 }; 481 482 pwm2: pwm2@40078200 { 483 compatible = "renesas,ra-pwm"; 484 divider = <RA_PWM_SOURCE_DIV_1>; 485 channel = <RA_PWM_CHANNEL_2>; 486 clocks = <&pclkd MSTPD 5>; 487 reg = <0x40078200 0x100>; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 pwm3: pwm3@40078300 { 493 compatible = "renesas,ra-pwm"; 494 divider = <RA_PWM_SOURCE_DIV_1>; 495 channel = <RA_PWM_CHANNEL_3>; 496 clocks = <&pclkd MSTPD 5>; 497 reg = <0x40078300 0x100>; 498 #pwm-cells = <3>; 499 status = "disabled"; 500 }; 501 502 pwm4: pwm4@40078400 { 503 compatible = "renesas,ra-pwm"; 504 divider = <RA_PWM_SOURCE_DIV_1>; 505 channel = <RA_PWM_CHANNEL_4>; 506 clocks = <&pclkd MSTPD 5>; 507 reg = <0x40078400 0x100>; 508 #pwm-cells = <3>; 509 status = "disabled"; 510 }; 511 512 pwm5: pwm5@40078500 { 513 compatible = "renesas,ra-pwm"; 514 divider = <RA_PWM_SOURCE_DIV_1>; 515 channel = <RA_PWM_CHANNEL_5>; 516 clocks = <&pclkd MSTPD 5>; 517 reg = <0x40078500 0x100>; 518 #pwm-cells = <3>; 519 status = "disabled"; 520 }; 521 522 pwm6: pwm6@40078600 { 523 compatible = "renesas,ra-pwm"; 524 divider = <RA_PWM_SOURCE_DIV_1>; 525 channel = <RA_PWM_CHANNEL_6>; 526 clocks = <&pclkd MSTPD 5>; 527 reg = <0x40078600 0x100>; 528 #pwm-cells = <3>; 529 status = "disabled"; 530 }; 531 532 pwm7: pwm7@40078700 { 533 compatible = "renesas,ra-pwm"; 534 divider = <RA_PWM_SOURCE_DIV_1>; 535 channel = <RA_PWM_CHANNEL_7>; 536 clocks = <&pclkd MSTPD 5>; 537 reg = <0x40078700 0x100>; 538 #pwm-cells = <3>; 539 status = "disabled"; 540 }; 541 542 pwm8: pwm8@40078800 { 543 compatible = "renesas,ra-pwm"; 544 divider = <RA_PWM_SOURCE_DIV_1>; 545 channel = <RA_PWM_CHANNEL_8>; 546 clocks = <&pclkd MSTPD 6>; 547 reg = <0x40078800 0x100>; 548 #pwm-cells = <3>; 549 status = "disabled"; 550 }; 551 552 pwm9: pwm9@40078900 { 553 compatible = "renesas,ra-pwm"; 554 divider = <RA_PWM_SOURCE_DIV_1>; 555 channel = <RA_PWM_CHANNEL_9>; 556 clocks = <&pclkd MSTPD 6>; 557 reg = <0x40078900 0x100>; 558 #pwm-cells = <3>; 559 status = "disabled"; 560 }; 561 562 pwm10: pwm10@40078a00 { 563 compatible = "renesas,ra-pwm"; 564 divider = <RA_PWM_SOURCE_DIV_1>; 565 channel = <RA_PWM_CHANNEL_10>; 566 clocks = <&pclkd MSTPD 6>; 567 reg = <0x40078a00 0x100>; 568 #pwm-cells = <3>; 569 status = "disabled"; 570 }; 571 572 pwm11: pwm11@40078b00 { 573 compatible = "renesas,ra-pwm"; 574 divider = <RA_PWM_SOURCE_DIV_1>; 575 channel = <RA_PWM_CHANNEL_11>; 576 clocks = <&pclkd MSTPD 6>; 577 reg = <0x40078b00 0x100>; 578 #pwm-cells = <3>; 579 status = "disabled"; 580 }; 581 582 pwm12: pwm12@40078c00 { 583 compatible = "renesas,ra-pwm"; 584 divider = <RA_PWM_SOURCE_DIV_1>; 585 channel = <RA_PWM_CHANNEL_12>; 586 clocks = <&pclkd MSTPD 6>; 587 reg = <0x40078c00 0x100>; 588 #pwm-cells = <3>; 589 status = "disabled"; 590 }; 591 }; 592}; 593 594&nvic { 595 arm,num-irq-priority-bits = <4>; 596}; 597
