Home
last modified time | relevance | path

Searched +full:tri +full:- +full:default (Results 1 – 25 of 34) sorted by relevance

12

/Zephyr-latest/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
[all …]
/Zephyr-latest/boards/digilent/arty_a7/dts/
Darty_a7_arm_designstart.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
16 /* Use DTCM as SRAM by default */
32 compatible = "gpio-leds";
104 compatible = "gpio-keys";
148 compatible = "arm,daplink-qspi-mux";
150 interrupt-parent = <&nvic>;
152 mux-gpios = <&daplink_gpio0 0 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
80 _ier = *reg_enable[IT8XXX2_IER_COUNT - 1]; in ite_intc_save_and_disable_interrupts()
125 /* critical section due to run a bit-wise OR operation */ in ite_intc_irq_enable()
144 /* critical section due to run a bit-wise OR operation */ in ite_intc_irq_disable()
158 volatile uint8_t *tri; in ite_intc_irq_polarity_set() local
165 tri = reg_ipolr[g]; in ite_intc_irq_polarity_set()
167 CLEAR_MASK(*tri, BIT(i)); in ite_intc_irq_polarity_set()
169 SET_MASK(*tri, BIT(i)); in ite_intc_irq_polarity_set()
171 tri = reg_ielmr[g]; in ite_intc_irq_polarity_set()
173 CLEAR_MASK(*tri, BIT(i)); in ite_intc_irq_polarity_set()
[all …]
/Zephyr-latest/drivers/bluetooth/hci/
DKconfig.nxp2 # Copyright 2023-2024 NXP
4 # SPDX-License-Identifier: Apache-2.0
37 default 512
41 default 4
45 default 768
52 default "NXP"
55 default n
58 default 84
62 default 256
65 default y
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_axi.c4 * SPDX-License-Identifier: Apache-2.0
54 uint32_t tri; member
67 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_read_data()
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
74 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
81 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_tri()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
88 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_pin_configure()
89 struct gpio_xlnx_axi_data *data = dev->data; in gpio_xlnx_axi_pin_configure()
[all …]
Dgpio_ite_it8xxx2_v2.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
19 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
80 const struct gpio_ite_cfg *gpio_config = dev->config; in gpio_ite_configure()
81 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr; in gpio_ite_configure()
82 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr; in gpio_ite_configure()
83 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr; in gpio_ite_configure()
84 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin; in gpio_ite_configure()
85 struct gpio_ite_data *data = dev->data; in gpio_ite_configure()
92 return -ENOTSUP; in gpio_ite_configure()
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnuvoton,npcx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
10 - bias-pull-down: Enable pull-down resistor.
11 - bias-pull-up: Enable pull-up resistor.
12 - drive-open-drain: Output driver is open-drain.
15 - pinmux-locked: Lock pinmux configuration for peripheral device
16 - pinmux-gpio: Inverse pinmux back to gpio
17 - psl-in-mode: Select the assertion detection mode of PSL input
18 - psl-in-pol: Select the assertion detection polarity of PSL input
23 #include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
26 internal 3.3V pull-up if its i2c frequency won't exceed 400kHz.
[all …]
Dxlnx,pinctrl-zynq.yaml2 # SPDX-License-Identifier: Apache-2.0
5 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
6 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
9 Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and
18 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
21 pinctrl_uart1_default: uart1-default {
29 slew-rate = <IO_SPEED_SLOW>;
30 power-source = <IO_STANDARD_LVCMOS18>;
33 conf-rx {
35 bias-high-impedance;
[all …]
/Zephyr-latest/soc/ite/ec/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
24 * pull-up/down, voltage selection, input.
41 * Pin pull-up/down config [ 4 : 5 ]
44 * Pin push-pull/open-drain [ 16 ]
46 * Pin drive current default [ 21 ]
60 /* Pin tri-state mode. */
63 /* Pin pull-up or pull-down */
73 /* Pin push-pull/open-drain mode */
[all …]
/Zephyr-latest/boards/nxp/frdm_rw612/doc/
Dindex.rst6 The RW612 is a highly integrated, low-power tri-radio wireless MCU with an
7 integrated 260 MHz ARM Cortex-M33 MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.3 / 802.15.4
11 The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface
12 with an on-the-fly decryption engine for securely accessing off-chip XIP flash.
15 operation in a space- and cost-efficient wireless MCU requiring only a single 3.3 V power supply.
20 - 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4
21 - 1.2 MB on-chip SRAM
26 +-----------+------------+-----------------------------------+
29 | NVIC | on-chip | nested vector interrupt controller|
30 +-----------+------------+-----------------------------------+
[all …]
/Zephyr-latest/subsys/mgmt/osdp/
DKconfig.pd4 # SPDX-License-Identifier: Apache-2.0
11 default 1
18 default 16
26 default 1
38 default "NONE"
43 channel with default SCBK. Once as secure channel is active with the
44 default key, the CP can send a KEYSET command to set new keys to the PD.
54 default 0x001A2B3C
61 default 1
68 default 1
[all …]
/Zephyr-latest/boards/nxp/rd_rw612_bga/doc/
Dindex.rst6 The RW612 is a highly integrated, low-power tri-radio wireless MCU with an
7 integrated 260 MHz ARM Cortex-M33 MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.3 / 802.15.4
11 The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface
12 with an on-the-fly decryption engine for securely accessing off-chip XIP flash.
15 operation in a space- and cost-efficient wireless MCU requiring only a single 3.3 V power supply.
20 - 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4
21 - 1.2 MB on-chip SRAM
26 +-----------+------------+-----------------------------------+
29 | NVIC | on-chip | nested vector interrupt controller|
30 +-----------+------------+-----------------------------------+
[all …]
/Zephyr-latest/drivers/spi/
Dspi_xlnx_axi_quadspi.c4 * SPDX-License-Identifier: Apache-2.0
105 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_read32()
107 return sys_read32(config->base + offset); in xlnx_quadspi_read32()
114 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_write32()
116 sys_write32(value, config->base + offset); in xlnx_quadspi_write32()
121 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_cs_control()
122 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_cs_control()
123 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_cs_control()
124 uint32_t spissr = BIT_MASK(config->num_ss_bits); in xlnx_quadspi_cs_control()
127 /* Skip slave select assert/de-assert in slave mode */ in xlnx_quadspi_cs_control()
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
53 * KSO push-pull/open-drain bit of KSO[15:0] control register
74 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
75 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set()
76 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
77 uint8_t pin = pins->pin; in pinctrl_it8xxx2_set()
78 volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin; in pinctrl_it8xxx2_set()
79 volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]); in pinctrl_it8xxx2_set()
80 volatile uint8_t *reg_pdsc = (uint8_t *)gpio->reg_pdsc; in pinctrl_it8xxx2_set()
82 /* Setting pull-up or pull-down. */ in pinctrl_it8xxx2_set()
[all …]
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h4 * SPDX-License-Identifier: Apache-2.0
34 /* Default SAF Map of eSPI TAG numbers to master numbers */
40 * Default QMSPI clock divider and chip select timing.
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
106 /* SAF Pre-fetch optimization mode */
112 * SAF Opcode 32-bit register value.
113 * Each byte contain a SPI flash 8-bit opcode.
117 * op0 = SPI flash write-enable opcode
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxc444/doc/
Dindex.rst6 FRDM-MCXC444 is a compact and scalable development board for rapid
8 for easy access to the MCU's I/Os, integrated open-standard serial
9 interfaces and on-board MCU-Link debugger.
10 The MCXC is a general purpose ultra-low-power MCU family,
16 - MCXC444VLH Arm Cortex-M0+ microcontroller running at 48 MHz
17 - 64LQFP package
18 - 256 KB flash
19 - 32 KB SRAM
20 - USB FS 2.0
21 - 2x low-power UART, 1x UART, 2x I2C, 2x SPI
[all …]
/Zephyr-latest/boards/nxp/frdm_kl25z/doc/
Dindex.rst6 The Freedom KL25Z is an ultra-low-cost development platform for
8 on ARM |reg| Cortex |reg|-M0+ processor.
10 The FRDM-KL25Z features include easy access to MCU I/O, battery-ready,
11 low-power operation, a standard-based form factor with expansion board
12 options and a built-in debug interface for flash programming and run-control.
17 - MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP
18 - On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED
19 - OpenSDA debug interface
21 For more information about the KL25Z SoC and FRDM-KL25Z board:
23 - `KL25Z Website`_
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h4 * SPDX-License-Identifier: Apache-2.0
33 /* Default SAF Map of eSPI TAG numbers to master numbers */
39 * Default QMSPI clock divider and chip select timing.
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
130 /* SAF Pre-fetch optimization mode */
136 * SAF Opcode 32-bit register value.
137 * Each byte contain a SPI flash 8-bit opcode.
[all …]
/Zephyr-latest/boards/nxp/lpcxpresso11u68/doc/
Dindex.rst7 on an ARM Cortex-M0+ core.
14 - LPC11U68 microcontroller in LQFP100 package
15 - ARM Cortex-M0+
16 - Memory:
18 - 256KB of flash memory
19 - 32KB of SRAM
20 - 2x2KB of additional SRAM
21 - 4 KB EEPROM
22 - USB:
24 - USB 2.0 Full-Speed device controller
[all …]
/Zephyr-latest/drivers/wifi/nxp/
DKconfig.nxp1 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 bool "NXP Wi-Fi driver support"
14 Enable NXP SoC Wi-Fi support.
25 default 50
28 bool "Custom NXP Wi-Fi part"
30 Customize NXP Wi-Fi chip support.
33 prompt "Select NXP Wi-Fi part"
36 Choose NXP Wi-Fi chip support.
39 bool "NXP RW610-based Chipset"
[all …]
/Zephyr-latest/drivers/dai/nxp/sai/
Dsai.h3 * SPDX-License-Identifier: Apache-2.0
51 /* used to convert the clock-names property into an array of clock names */
72 /* used to convert a clock-names property into an array of clock names. If the
89 /* used to parse the tx-fifo-watermark property. If said property is not
97 /* used to parse the rx-fifo-watermark property. If said property is not
107 POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->TDR[idx]))
111 POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->RDR[idx]))
113 /* internal macro used to retrieve the default TX/RX FIFO's size (in FIFO words) */
190 ((dir) == DAI_DIR_RX ? (UINT_TO_I2S(regmap)->RCSR & I2S_RCSR_RE_MASK) : \
191 (UINT_TO_I2S(regmap)->TCSR & I2S_TCSR_TE_MASK))
[all …]
/Zephyr-latest/boards/nxp/lpcxpresso51u68/doc/
Dindex.rst7 on an ARM CORTEX-M0+ core.
12 - LPC51U68 M0+ running at up to 150 MHz
13 - Memory
15 - 256KB of flash memory
16 - 96KB of SRAM
17 - On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol
18 support, can debug the on-board LPC51U68 or an external target
19 - External debug probe option
20 - Tri-color LED, target reset, ISP & interrupt/user buttons for easy testing of
22 - Expansion options based on Arduino UNO and PMOD™, plus additional expansion
[all …]
/Zephyr-latest/boards/nxp/lpcxpresso55s06/doc/
Dindex.rst7 of the LPC55S0x/LPC550x MCU family, based on the Arm® Cortex®-M33
16 - LPC55S06 Arm® Cortex®-M33 microcontroller running at up to 96 MHz
17 - 256 KB flash and 96 KB SRAM on-chip
18 - LPC-Link2 debug high speed USB probe with VCOM port
19 - MikroElektronika Click expansion option
20 - LPCXpresso expansion connectors compatible with Arduino UNO
21 - PMod compatible expansion / host connector
22 - Reset, ISP, wake, and user buttons for easy testing of software functionality
23 - Tri-color LED
24 - UART header for external serial to USB cable
[all …]
/Zephyr-latest/boards/nxp/frdm_k82f/doc/
Dindex.rst6 The FRDM-K82F is a low-cost development platform for Kinetis K80, K81,
9 - Form-factor compatible with the Arduino R3 pin layout
10 - Peripherals enable rapid prototyping, including a six-axis digital
12 tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb
14 with Bluetooth and 2.4 GHz radio add-on modules
15 - OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter
17 flash programming, and run-control debugging
22 - MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power,
23 crystal-less USB, and 100 Low profile Quad Flat Package (LQFP))
24 - Dual role USB interface with micro-B USB connector
[all …]
/Zephyr-latest/boards/nxp/lpcxpresso54114/doc/
Dindex.rst7 prototyping with the low-power LPC54110 family of MCUs. LPCXpresso* is a
8 low-cost development platform available from NXP supporting NXP's ARM-based
9 microcontrollers. LPCXpresso is an end-to-end solution enabling embedded
16 - LPC54114 dual-core (M4F and dual M0) MCU running at up to 100 MHz
17 - On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol
18 support, can debug the on-board LPC54114 or an external target
19 - External debug probe option
20 - Tri-color LED, target Reset, ISP & interrupt/user buttons for easy testing of
22 - Expansion options based on Arduino UNO and Pmod™, plus additional expansion
24 - On-board 1.8 V and 3.3 V regulators plus external power supply option
[all …]

12