1 /*
2 * Copyright (c) 2022 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_pinctrl_func
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/pinctrl.h>
11 #include <zephyr/logging/log.h>
12
13 #include <chip_chipregs.h>
14
15 LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
16
17 #define GPIO_IT8XXX2_REG_BASE \
18 ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
19 #define GPIO_GROUP_MEMBERS 8
20
21 struct pinctrl_it8xxx2_gpio {
22 /* gpio port control register (byte mapping to pin) */
23 uint8_t *reg_gpcr;
24 /* port driving select control */
25 uint8_t *reg_pdsc;
26 /* function 3 general control register */
27 uintptr_t func3_gcr[GPIO_GROUP_MEMBERS];
28 /* function 3 enable mask */
29 uint8_t func3_en_mask[GPIO_GROUP_MEMBERS];
30 /* function 3 external control register */
31 uintptr_t func3_ext[GPIO_GROUP_MEMBERS];
32 /* function 3 external mask */
33 uint8_t func3_ext_mask[GPIO_GROUP_MEMBERS];
34 /* function 4 general control register */
35 uintptr_t func4_gcr[GPIO_GROUP_MEMBERS];
36 /* function 4 enable mask */
37 uint8_t func4_en_mask[GPIO_GROUP_MEMBERS];
38 /* Input voltage selection */
39 uintptr_t volt_sel[GPIO_GROUP_MEMBERS];
40 /* Input voltage selection mask */
41 uint8_t volt_sel_mask[GPIO_GROUP_MEMBERS];
42 };
43
44 struct pinctrl_it8xxx2_ksi_kso {
45 /*
46 * KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
47 * (bit mapping to pin)
48 */
49 uint8_t *reg_gctrl;
50 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
51 uint8_t *reg_ctrl;
52 /*
53 * KSO push-pull/open-drain bit of KSO[15:0] control register
54 * (this bit apply to all pins)
55 */
56 int pp_od_mask;
57 /*
58 * KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
59 * (this bit apply to all pins)
60 */
61 int pullup_mask;
62 };
63
64 struct pinctrl_it8xxx2_config {
65 bool gpio_group;
66 union {
67 struct pinctrl_it8xxx2_gpio gpio;
68 struct pinctrl_it8xxx2_ksi_kso ksi_kso;
69 };
70 };
71
pinctrl_it8xxx2_set(const pinctrl_soc_pin_t * pins)72 static int pinctrl_it8xxx2_set(const pinctrl_soc_pin_t *pins)
73 {
74 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
75 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
76 uint32_t pincfg = pins->pincfg;
77 uint8_t pin = pins->pin;
78 volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
79 volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]);
80 volatile uint8_t *reg_pdsc = (uint8_t *)gpio->reg_pdsc;
81
82 /* Setting pull-up or pull-down. */
83 switch (IT8XXX2_DT_PINCFG_PUPDR(pincfg)) {
84 case IT8XXX2_PULL_PIN_DEFAULT:
85 /* No pull-up or pull-down */
86 *reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
87 GPCR_PORT_PIN_MODE_PULLDOWN);
88 break;
89 case IT8XXX2_PULL_UP:
90 *reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
91 ~GPCR_PORT_PIN_MODE_PULLDOWN;
92 break;
93 case IT8XXX2_PULL_DOWN:
94 *reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
95 ~GPCR_PORT_PIN_MODE_PULLUP;
96 break;
97 default:
98 LOG_ERR("This pull level is not supported.");
99 return -EINVAL;
100 }
101
102 /*
103 * Since not all GPIOs support voltage selection, configure voltage
104 * selection register only if it is present.
105 */
106 if (reg_volt_sel != NULL) {
107 /* Setting voltage 3.3V or 1.8V. */
108 switch (IT8XXX2_DT_PINCFG_VOLTAGE(pincfg)) {
109 case IT8XXX2_VOLTAGE_3V3:
110 /* Input voltage selection 3.3V. */
111 *reg_volt_sel &= ~gpio->volt_sel_mask[pin];
112 break;
113 case IT8XXX2_VOLTAGE_1V8:
114 __ASSERT(!(IT8XXX2_DT_PINCFG_PUPDR(pincfg)
115 == IT8XXX2_PULL_UP),
116 "Don't enable internal pullup if 1.8V voltage is used");
117 /* Input voltage selection 1.8V. */
118 *reg_volt_sel |= gpio->volt_sel_mask[pin];
119 break;
120 default:
121 LOG_ERR("The voltage selection is not supported");
122 return -EINVAL;
123 }
124 }
125
126 /* Setting tri-state mode. */
127 if (IT8XXX2_DT_PINCFG_IMPEDANCE(pincfg)) {
128 *reg_gpcr |= (GPCR_PORT_PIN_MODE_PULLUP |
129 GPCR_PORT_PIN_MODE_PULLDOWN);
130 }
131
132 /* Driving current selection. */
133 if (reg_pdsc != NULL &&
134 IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) != IT8XXX2_DRIVE_DEFAULT) {
135 if (IT8XXX2_DT_PINCFG_DRIVE_CURRENT(pincfg) & IT8XXX2_PDSCX_MASK) {
136 /* Driving current selects low. */
137 *reg_pdsc |= BIT(pin);
138 } else {
139 /* Driving current selects high. */
140 *reg_pdsc &= ~BIT(pin);
141 }
142 }
143
144 return 0;
145 }
146
pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t * pins)147 static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
148 {
149 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
150 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);
151 uint8_t pin = pins->pin;
152 volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
153 volatile uint8_t *reg_func3_gcr = (uint8_t *)(gpio->func3_gcr[pin]);
154 volatile uint8_t *reg_func4_gcr = (uint8_t *)(gpio->func4_gcr[pin]);
155 volatile uint8_t *reg_func3_ext = (uint8_t *)(gpio->func3_ext[pin]);
156
157 /* Handle PIN configuration. */
158 if (pinctrl_it8xxx2_set(pins)) {
159 LOG_ERR("Pin configuration is invalid.");
160 return -EINVAL;
161 }
162
163 /*
164 * Default input mode prevents leakage during changes to extended
165 * setting (e.g. enabling i2c functionality on GPIO E1/E2 on IT82002)
166 */
167 *reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
168 ~GPCR_PORT_PIN_MODE_OUTPUT;
169
170 /*
171 * If pincfg is input, we don't need to handle
172 * alternate function.
173 */
174 if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) {
175 return 0;
176 }
177
178 /*
179 * Handle alternate function.
180 */
181 if (reg_func3_gcr != NULL) {
182 *reg_func3_gcr &= ~gpio->func3_en_mask[pin];
183 }
184 /* Ensure that func3-ext setting is in default state. */
185 if (reg_func3_ext != NULL) {
186 *reg_func3_ext &= ~gpio->func3_ext_mask[pin];
187 }
188
189 switch (pins->alt_func) {
190 case IT8XXX2_ALT_FUNC_1:
191 /* Func1: Alternate function will be set below. */
192 break;
193 case IT8XXX2_ALT_FUNC_2:
194 /* Func2: WUI function: pin has been set as input above.*/
195 return 0;
196 case IT8XXX2_ALT_FUNC_3:
197 /*
198 * Func3: In addition to the alternate setting above,
199 * Func3 also need to set the general control.
200 */
201 if (reg_func3_gcr != NULL) {
202 *reg_func3_gcr |= gpio->func3_en_mask[pin];
203 }
204 /* Func3-external: Some pins require external setting. */
205 if (reg_func3_ext != NULL) {
206 *reg_func3_ext |= gpio->func3_ext_mask[pin];
207 }
208 break;
209 case IT8XXX2_ALT_FUNC_4:
210 /*
211 * Func4: In addition to the alternate setting above,
212 * Func4 also need to set the general control.
213 */
214 *reg_func4_gcr |= gpio->func4_en_mask[pin];
215 break;
216 case IT8XXX2_ALT_DEFAULT:
217 *reg_func3_gcr &= ~gpio->func3_en_mask[pin];
218 *reg_func4_gcr &= ~gpio->func4_en_mask[pin];
219 return 0;
220 default:
221 LOG_ERR("This function is not supported.");
222 return -EINVAL;
223 }
224
225 /* Common settings for alternate function. */
226 *reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
227 GPCR_PORT_PIN_MODE_OUTPUT);
228
229 return 0;
230 }
231
pinctrl_kscan_it8xxx2_set(const pinctrl_soc_pin_t * pins)232 static int pinctrl_kscan_it8xxx2_set(const pinctrl_soc_pin_t *pins)
233 {
234 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
235 const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
236 volatile uint8_t *reg_ctrl = ksi_kso->reg_ctrl;
237 uint8_t pullup_mask = ksi_kso->pullup_mask;
238 uint8_t pp_od_mask = ksi_kso->pp_od_mask;
239 uint32_t pincfg = pins->pincfg;
240
241 /*
242 * Enable or disable internal pull-up (this bit apply to all pins):
243 * If KSI[7:0]/KSO[15:0] is in KBS mode , setting 1 enables the internal
244 * pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
245 * If KSI[7:0]/KSO[15:0] is in GPIO mode, then this bit is always disabled.
246 */
247 switch (IT8XXX2_DT_PINCFG_PULLUP(pincfg)) {
248 case IT8XXX2_PULL_PIN_DEFAULT:
249 /* Disable internal pulll-up */
250 *reg_ctrl &= ~pullup_mask;
251 break;
252 case IT8XXX2_PULL_UP:
253 *reg_ctrl |= pullup_mask;
254 break;
255 default:
256 LOG_ERR("This pull level is not supported.");
257 return -EINVAL;
258 }
259
260 /*
261 * Set push-pull or open-drain mode (this bit apply to all pins):
262 * KSI[7:0] doesn't support push-pull and open-drain settings in kbs mode.
263 * If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
264 * setting 0 selects push-pull mode.
265 * If KSO[15:0] is in GPIO mode, then this bit is always disabled.
266 */
267 if (pp_od_mask != NO_FUNC) {
268 switch (IT8XXX2_DT_PINCFG_PP_OD(pincfg)) {
269 case IT8XXX2_PUSH_PULL:
270 *reg_ctrl &= ~pp_od_mask;
271 break;
272 case IT8XXX2_OPEN_DRAIN:
273 *reg_ctrl |= pp_od_mask;
274 break;
275 default:
276 LOG_ERR("This pull mode is not supported.");
277 return -EINVAL;
278 }
279 }
280
281 return 0;
282 }
283
pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t * pins)284 static int pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
285 {
286 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
287 const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
288
289 /* Set a pin of KSI[7:0]/KSO[15:0] to pullup, push-pull/open-drain */
290 if (pinctrl_kscan_it8xxx2_set(pins)) {
291 return -EINVAL;
292 }
293
294 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
295 uint8_t pin_mask = BIT(pins->pin);
296 volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl;
297
298 switch (pins->alt_func) {
299 case IT8XXX2_ALT_FUNC_1:
300 /* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
301 *reg_gctrl &= ~pin_mask;
302 break;
303 case IT8XXX2_ALT_DEFAULT:
304 /* Set a pin of KSI[7:0]/KSO[15:0] to gpio mode */
305 *reg_gctrl |= pin_mask;
306 break;
307 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
308 uint8_t pin = pins->pin;
309 volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl + pin;
310
311 switch (pins->alt_func) {
312 case IT8XXX2_ALT_FUNC_1:
313 /* Set a pin of KSI[7:0]/KSO[15:0] to kbs mode */
314 *reg_gctrl &= ~(GPCR_PORT_PIN_MODE_INPUT |
315 GPCR_PORT_PIN_MODE_OUTPUT);
316 break;
317 case IT8XXX2_ALT_DEFAULT:
318 /* Set a pin of KSI[7:0]/KSO[15:0] to gpio mode */
319 *reg_gctrl = (*reg_gctrl | GPCR_PORT_PIN_MODE_INPUT) &
320 ~GPCR_PORT_PIN_MODE_OUTPUT;
321 break;
322 #endif
323 default:
324 LOG_ERR("Alternate function not supported");
325 return -ENOTSUP;
326 }
327
328 return 0;
329 }
330
331 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
332 uintptr_t reg)
333 {
334 ARG_UNUSED(reg);
335 const struct pinctrl_it8xxx2_config *pinctrl_config;
336 int status;
337
338 for (uint8_t i = 0U; i < pin_cnt; i++) {
339 pinctrl_config = pins[i].pinctrls->config;
340
341 if (pinctrl_config->gpio_group) {
342 status = pinctrl_gpio_it8xxx2_configure_pins(&pins[i]);
343 } else {
344 status = pinctrl_kscan_it8xxx2_configure_pins(&pins[i]);
345 }
346
347 if (status < 0) {
348 LOG_ERR("%s pin%d configuration is invalid.",
349 pins[i].pinctrls->name, pins[i].pin);
350 return status;
351 }
352 }
353
354 return 0;
355 }
356
357 static int pinctrl_it8xxx2_init(const struct device *dev)
358 {
359 struct gpio_it8xxx2_regs *const gpio_base = GPIO_IT8XXX2_REG_BASE;
360
361 /*
362 * The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
363 * If LPC reset is enabled on GPB7, we have to clear bit2:1
364 * to 00b.
365 */
366 gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
367
368 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
369 #if defined(CONFIG_I2C_ITE_ENHANCE) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c5))
370 const struct gpio_dt_spec scl_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), scl_gpios);
371 const struct gpio_dt_spec sda_gpios = GPIO_DT_SPEC_GET(DT_NODELABEL(i2c5), sda_gpios);
372
373 /*
374 * When setting these pins as I2C alternate mode and then setting
375 * GCR7 or func3-ext of GPIO extended, it will cause leakage.
376 * In order to prevent leakage, it must be set to GPIO INPUT mode.
377 */
378 /* Set I2C5 SCL as GPIO input to prevent leakage */
379 gpio_pin_configure_dt(&scl_gpios, GPIO_INPUT);
380 /* Set I2C5 SDA as GPIO input to prevent leakage */
381 gpio_pin_configure_dt(&sda_gpios, GPIO_INPUT);
382 #endif
383 /*
384 * Swap the default I2C2 SMCLK2/SMDAT2 pins from GPC7/GPD0 to GPF6/GPF7,
385 * and I2C3 SMCLK3/SMDAT3 pins from GPB2/GPB5 to GPH1/GPH2,
386 * and I2C5 SMCLK5/SMDAT5 pins from GPE1/GPE2 to GPA4/GPA5,
387 */
388 gpio_base->GPIO_GCR7 &= ~(IT8XXX2_GPIO_SMB2PS |
389 IT8XXX2_GPIO_SMB3PS |
390 IT8XXX2_GPIO_SMB5PS);
391 #endif
392 return 0;
393 }
394
395 #define INIT_UNION_CONFIG(inst) \
396 COND_CODE_1(DT_INST_PROP(inst, gpio_group), \
397 (.gpio = { \
398 .reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
399 .reg_pdsc = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
400 .func3_gcr = DT_INST_PROP(inst, func3_gcr), \
401 .func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
402 .func3_ext = DT_INST_PROP_OR(inst, func3_ext, {0}), \
403 .func3_ext_mask = DT_INST_PROP_OR(inst, func3_ext_mask, {0}), \
404 .func4_gcr = DT_INST_PROP(inst, func4_gcr), \
405 .func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
406 .volt_sel = DT_INST_PROP(inst, volt_sel), \
407 .volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
408 }), \
409 (.ksi_kso = { \
410 .reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
411 .reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
412 .pp_od_mask = (uint8_t)DT_INST_PROP(inst, pp_od_mask), \
413 .pullup_mask = (uint8_t)DT_INST_PROP(inst, pullup_mask), \
414 }) \
415 )
416
417 #define PINCTRL_ITE_INIT(inst) \
418 static const struct pinctrl_it8xxx2_config pinctrl_it8xxx2_cfg_##inst = { \
419 .gpio_group = DT_INST_PROP(inst, gpio_group), \
420 { \
421 INIT_UNION_CONFIG(inst) \
422 } \
423 }; \
424 \
425 DEVICE_DT_INST_DEFINE(inst, &pinctrl_it8xxx2_init, \
426 NULL, \
427 NULL, \
428 &pinctrl_it8xxx2_cfg_##inst, \
429 PRE_KERNEL_1, \
430 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
431 NULL);
432 DT_INST_FOREACH_STATUS_OKAY(PINCTRL_ITE_INIT)
433
