Lines Matching +full:tri +full:- +full:default
4 * SPDX-License-Identifier: Apache-2.0
105 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_read32()
107 return sys_read32(config->base + offset); in xlnx_quadspi_read32()
114 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_write32()
116 sys_write32(value, config->base + offset); in xlnx_quadspi_write32()
121 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_cs_control()
122 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_cs_control()
123 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_cs_control()
124 uint32_t spissr = BIT_MASK(config->num_ss_bits); in xlnx_quadspi_cs_control()
127 /* Skip slave select assert/de-assert in slave mode */ in xlnx_quadspi_cs_control()
132 /* SPISSR is one-hot, active-low */ in xlnx_quadspi_cs_control()
133 spissr &= ~BIT(ctx->config->slave); in xlnx_quadspi_cs_control()
134 } else if (ctx->config->operation & SPI_HOLD_ON_CS) { in xlnx_quadspi_cs_control()
135 /* Skip slave select de-assert */ in xlnx_quadspi_cs_control()
146 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_configure()
147 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_configure()
148 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_configure()
161 if (spi_cfg->operation & SPI_HALF_DUPLEX) { in xlnx_quadspi_configure()
162 LOG_ERR("Half-duplex not supported"); in xlnx_quadspi_configure()
163 return -ENOTSUP; in xlnx_quadspi_configure()
166 if (spi_cfg->slave >= config->num_ss_bits) { in xlnx_quadspi_configure()
168 spi_cfg->slave, config->num_ss_bits); in xlnx_quadspi_configure()
169 return -ENOTSUP; in xlnx_quadspi_configure()
172 if (spi_cfg->operation & SPI_CS_ACTIVE_HIGH) { in xlnx_quadspi_configure()
174 return -ENOTSUP; in xlnx_quadspi_configure()
178 (spi_cfg->operation & SPI_OP_MODE_SLAVE)) { in xlnx_quadspi_configure()
180 return -ENOTSUP; in xlnx_quadspi_configure()
183 word_size = SPI_WORD_SIZE_GET(spi_cfg->operation); in xlnx_quadspi_configure()
184 if (word_size != (config->num_xfer_bytes * 8)) { in xlnx_quadspi_configure()
186 word_size, config->num_xfer_bytes); in xlnx_quadspi_configure()
187 return -ENOTSUP; in xlnx_quadspi_configure()
195 (spi_cfg->operation & SPI_OP_MODE_SLAVE) == 0U) { in xlnx_quadspi_configure()
199 if (spi_cfg->operation & SPI_MODE_CPOL) { in xlnx_quadspi_configure()
203 if (spi_cfg->operation & SPI_MODE_CPHA) { in xlnx_quadspi_configure()
207 if (spi_cfg->operation & SPI_MODE_LOOP) { in xlnx_quadspi_configure()
211 if (spi_cfg->operation & SPI_TRANSFER_LSB) { in xlnx_quadspi_configure()
217 * configuration. Tri-state SPI IOs on error. in xlnx_quadspi_configure()
224 ctx->config = NULL; in xlnx_quadspi_configure()
225 return -ENOTSUP; in xlnx_quadspi_configure()
228 ctx->config = spi_cfg; in xlnx_quadspi_configure()
235 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_start_tx()
236 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_start_tx()
237 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_start_tx()
242 uint32_t fifo_avail_words = config->fifo_size ? config->fifo_size : 1; in xlnx_quadspi_start_tx()
246 /* All done, de-assert slave select */ in xlnx_quadspi_start_tx()
249 if ((ctx->config->operation & SPI_HOLD_ON_CS) == 0U) { in xlnx_quadspi_start_tx()
250 /* Tri-state SPI IOs */ in xlnx_quadspi_start_tx()
272 while (xfer_len--) { in xlnx_quadspi_start_tx()
274 switch (config->num_xfer_bytes) { in xlnx_quadspi_start_tx()
276 dtr = UNALIGNED_GET((uint8_t *)(ctx->tx_buf)); in xlnx_quadspi_start_tx()
279 dtr = UNALIGNED_GET((uint16_t *)(ctx->tx_buf)); in xlnx_quadspi_start_tx()
282 dtr = UNALIGNED_GET((uint32_t *)(ctx->tx_buf)); in xlnx_quadspi_start_tx()
284 default: in xlnx_quadspi_start_tx()
293 spi_context_update_tx(ctx, config->num_xfer_bytes, 1); in xlnx_quadspi_start_tx()
295 if (--fifo_avail_words == 0) { in xlnx_quadspi_start_tx()
300 if (!config->fifo_size) { in xlnx_quadspi_start_tx()
303 fifo_avail_words = config->fifo_size; in xlnx_quadspi_start_tx()
305 fifo_avail_words = config->fifo_size - in xlnx_quadspi_start_tx()
306 xlnx_quadspi_read32(dev, SPI_TX_FIFO_OCR_OFFSET) - 1; in xlnx_quadspi_start_tx()
318 if ((ctx->config->operation & SPI_HOLD_ON_CS) == 0U) { in xlnx_quadspi_start_tx()
319 /* Tri-state SPI IOs */ in xlnx_quadspi_start_tx()
325 spi_context_complete(ctx, dev, -ENOTSUP); in xlnx_quadspi_start_tx()
339 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_read_fifo()
340 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_read_fifo()
341 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_read_fifo()
344 uint32_t rx_fifo_words = config->fifo_size ? in xlnx_quadspi_read_fifo()
352 switch (config->num_xfer_bytes) { in xlnx_quadspi_read_fifo()
354 UNALIGNED_PUT(drr, (uint8_t *)ctx->rx_buf); in xlnx_quadspi_read_fifo()
357 UNALIGNED_PUT(drr, (uint16_t *)ctx->rx_buf); in xlnx_quadspi_read_fifo()
360 UNALIGNED_PUT(drr, (uint32_t *)ctx->rx_buf); in xlnx_quadspi_read_fifo()
362 default: in xlnx_quadspi_read_fifo()
367 spi_context_update_rx(ctx, config->num_xfer_bytes, 1); in xlnx_quadspi_read_fifo()
369 if (--rx_fifo_words == 0) { in xlnx_quadspi_read_fifo()
371 rx_fifo_words = config->fifo_size ? in xlnx_quadspi_read_fifo()
385 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_transceive()
386 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_transceive()
387 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_transceive()
398 config->num_xfer_bytes); in xlnx_quadspi_transceive()
403 k_event_clear(&data->dtr_empty, 1); in xlnx_quadspi_transceive()
414 if (!k_event_wait(&data->dtr_empty, 1, false, in xlnx_quadspi_transceive()
418 spi_context_complete(ctx, dev, -ETIMEDOUT); in xlnx_quadspi_transceive()
456 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_release()
457 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_release()
460 /* Force slave select de-assert */ in xlnx_quadspi_release()
461 xlnx_quadspi_write32(dev, BIT_MASK(config->num_ss_bits), SPISSR_OFFSET); in xlnx_quadspi_release()
463 /* Tri-state SPI IOs */ in xlnx_quadspi_release()
468 spi_context_unlock_unconditionally(&data->ctx); in xlnx_quadspi_release()
475 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_isr()
490 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_isr()
492 if (ctx->asynchronous) { in xlnx_quadspi_isr()
498 k_event_post(&data->dtr_empty, 1); in xlnx_quadspi_isr()
507 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_startup_block_workaround()
508 uint32_t spissr = BIT_MASK(config->num_ss_bits); in xlnx_quadspi_startup_block_workaround()
533 return -EIO; in xlnx_quadspi_startup_block_workaround()
542 spissr = BIT_MASK(config->num_ss_bits); in xlnx_quadspi_startup_block_workaround()
555 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_init()
556 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_init()
558 k_event_init(&data->dtr_empty); in xlnx_quadspi_init()
563 config->irq_config_func(dev); in xlnx_quadspi_init()
565 err = spi_context_cs_configure_all(&data->ctx); in xlnx_quadspi_init()
570 spi_context_unlock_unconditionally(&data->ctx); in xlnx_quadspi_init()
573 if (config->startup_block) { in xlnx_quadspi_init()