1/* 2 * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <zephyr/dt-bindings/gpio/gpio.h> 8#include <mem.h> 9#include <zephyr/dt-bindings/input/input-event-codes.h> 10 11/ { 12 chosen { 13 zephyr,console = &uartlite0; 14 zephyr,shell-uart = &uartlite0; 15 zephyr,flash = &itcm; 16 /* Use DTCM as SRAM by default */ 17 zephyr,sram = &dtcm; 18 }; 19 20 aliases { 21 led0 = &led_ld4; 22 led1 = &led_ld5; 23 led2 = &led_ld6; 24 led3 = &led_ld7; 25 sw0 = &sw0; 26 sw1 = &sw1; 27 sw2 = &sw2; 28 sw3 = &sw3; 29 }; 30 31 leds { 32 compatible = "gpio-leds"; 33 led_ld0_red: led_ld0_red { 34 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 35 label = "LED LD0 RED"; 36 }; 37 led_ld0_green: led_ld0_green { 38 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 39 label = "LED LD0 GREEN"; 40 }; 41 led_ld0_blue: led_ld0_blue { 42 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 43 label = "LED LD0 BLUE"; 44 }; 45 46 led_ld1_red: led_ld1_red { 47 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 48 label = "LED LD1 RED"; 49 }; 50 led_ld1_green: led_ld1_green { 51 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 52 label = "LED LD1 GREEN"; 53 }; 54 led_ld1_blue: led_ld1_blue { 55 gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 56 label = "LED LD1 BLUE"; 57 }; 58 59 led_ld2_red: led_ld2_red { 60 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 61 label = "LED LD2 RED"; 62 }; 63 led_ld2_green: led_ld2_green { 64 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 65 label = "LED LD2 GREEN"; 66 }; 67 led_ld2_blue: led_ld2_blue { 68 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 69 label = "LED LD2 BLUE"; 70 }; 71 72 led_ld3_red: led_ld3_red { 73 gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 74 label = "LED LD3 RED"; 75 }; 76 led_ld3_green: led_ld3_green { 77 gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 78 label = "LED LD3 GREEN"; 79 }; 80 led_ld3_blue: led_ld3_blue { 81 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 82 label = "LED LD3 BLUE"; 83 }; 84 85 led_ld4: led_ld4 { 86 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 87 label = "LED LD4"; 88 }; 89 led_ld5: led_ld5 { 90 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; 91 label = "LED LD5"; 92 }; 93 led_ld6: led_ld6 { 94 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; 95 label = "LED LD6"; 96 }; 97 led_ld7: led_ld7 { 98 gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 99 label = "LED LD7"; 100 }; 101 }; 102 103 gpio_keys { 104 compatible = "gpio-keys"; 105 sw0: sw0 { 106 gpios = <&gpio0_2 0 GPIO_ACTIVE_HIGH>; 107 label = "SW0"; 108 zephyr,code = <INPUT_KEY_0>; 109 }; 110 sw1: sw1 { 111 gpios = <&gpio0_2 1 GPIO_ACTIVE_HIGH>; 112 label = "SW1"; 113 zephyr,code = <INPUT_KEY_1>; 114 }; 115 sw2: sw2 { 116 gpios = <&gpio0_2 2 GPIO_ACTIVE_HIGH>; 117 label = "SW2"; 118 zephyr,code = <INPUT_KEY_2>; 119 }; 120 sw3: sw3 { 121 gpios = <&gpio0_2 3 GPIO_ACTIVE_HIGH>; 122 label = "SW3"; 123 zephyr,code = <INPUT_KEY_3>; 124 }; 125 btn0: btn0 { 126 gpios = <&gpio1_2 0 GPIO_ACTIVE_HIGH>; 127 label = "BTN0"; 128 zephyr,code = <INPUT_KEY_4>; 129 }; 130 btn1: btn1 { 131 gpios = <&gpio1_2 1 GPIO_ACTIVE_HIGH>; 132 label = "BTN1"; 133 zephyr,code = <INPUT_KEY_5>; 134 }; 135 btn2: btn2 { 136 gpios = <&gpio1_2 2 GPIO_ACTIVE_HIGH>; 137 label = "BTN2"; 138 zephyr,code = <INPUT_KEY_6>; 139 }; 140 btn3: btn3 { 141 gpios = <&gpio1_2 3 GPIO_ACTIVE_HIGH>; 142 label = "BTN3"; 143 zephyr,code = <INPUT_KEY_7>; 144 }; 145 }; 146 147 daplink_qspi_mux: daplink_qspi_mux { 148 compatible = "arm,daplink-qspi-mux"; 149 status = "disabled"; 150 interrupt-parent = <&nvic>; 151 interrupts = <7 0>; 152 mux-gpios = <&daplink_gpio0 0 GPIO_ACTIVE_HIGH>; 153 }; 154 155 soc { 156 daplink_gpio0: gpio@40010000 { 157 compatible = "xlnx,xps-gpio-1.00.a"; 158 status = "disabled"; 159 reg = <0x40010000 0x10000>; 160 gpio-controller; 161 #gpio-cells = <2>; 162 163 xlnx,all-inputs = <0x0>; 164 xlnx,all-outputs = <0x0>; 165 xlnx,dout-default = <0x0>; 166 xlnx,gpio-width = <0x20>; 167 xlnx,is-dual = <0x0>; 168 xlnx,tri-default = <0xffffffff>; 169 }; 170 171 daplink_quad_spi0: spi@40020000 { 172 compatible = "xlnx,xps-spi-2.00.a"; 173 status = "disabled"; 174 reg = <0x40020000 0x10000>; 175 interrupts = <4 0>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 179 xlnx,num-ss-bits = <0x1>; 180 xlnx,num-transfer-bits = <0x8>; 181 }; 182 183 daplink_single_spi0: spi@40030000 { 184 compatible = "xlnx,xps-spi-2.00.a"; 185 status = "disabled"; 186 reg = <0x40030000 0x10000>; 187 interrupts = <5 0>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 xlnx,num-ss-bits = <0x1>; 192 xlnx,num-transfer-bits = <0x8>; 193 }; 194 195 uartlite0: uartlite@40100000 { 196 compatible = "xlnx,xps-uartlite-1.00.a"; 197 interrupts = <0 0>; 198 reg = <0x40100000 0x10000>; 199 }; 200 201 gpio0: gpio@40110000 { 202 compatible = "xlnx,xps-gpio-1.00.a"; 203 interrupts = <1 0>; 204 reg = <0x40110000 0x10000>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 208 xlnx,all-inputs = <0x0>; 209 xlnx,all-inputs-2 = <0x1>; 210 xlnx,all-outputs = <0x0>; 211 xlnx,all-outputs-2 = <0x0>; 212 xlnx,dout-default = <0x0>; 213 xlnx,dout-default-2 = <0x0>; 214 xlnx,gpio-width = <0x4>; 215 xlnx,gpio2-width = <0x4>; 216 xlnx,is-dual = <0x1>; 217 xlnx,tri-default = <0xffffffff>; 218 xlnx,tri-default-2 = <0xffffffff>; 219 220 gpio0_2: gpio2 { 221 compatible = "xlnx,xps-gpio-1.00.a-gpio2"; 222 gpio-controller; 223 #gpio-cells = <2>; 224 }; 225 }; 226 227 gpio1: gpio@40120000 { 228 compatible = "xlnx,xps-gpio-1.00.a"; 229 interrupts = <2 0>; 230 reg = <0x40120000 0x10000>; 231 gpio-controller; 232 #gpio-cells = <2>; 233 234 xlnx,all-inputs = <0x0>; 235 xlnx,all-inputs-2 = <0x1>; 236 xlnx,all-outputs = <0x0>; 237 xlnx,all-outputs-2 = <0x0>; 238 xlnx,dout-default = <0x0>; 239 xlnx,dout-default-2 = <0x0>; 240 xlnx,gpio-width = <0xc>; 241 xlnx,gpio2-width = <0x4>; 242 xlnx,is-dual = <0x1>; 243 xlnx,tri-default = <0xffffffff>; 244 xlnx,tri-default-2 = <0xffffffff>; 245 246 gpio1_2: gpio2 { 247 compatible = "xlnx,xps-gpio-1.00.a-gpio2"; 248 gpio-controller; 249 #gpio-cells = <2>; 250 }; 251 }; 252 253 quad_spi0: spi@40130000 { 254 compatible = "xlnx,xps-spi-2.00.a"; 255 reg = <0x40130000 0x10000>; 256 interrupts = <3 0>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 xlnx,num-ss-bits = <0x1>; 261 xlnx,num-transfer-bits = <0x8>; 262 263 flash0: flash@0 { 264 compatible = "micron,n25q128a","jedec,spi-nor"; 265 reg = <0>; 266 spi-max-frequency = <108000000>; 267 size = <DT_SIZE_M(128)>; 268 jedec-id = [20 ba 18]; 269 270 partitions { 271 compatible = "fixed-partitions"; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 275 fpga_bitstream_partition: partition@0 { 276 label = "fpga_bitstream"; 277 /* From Xilinx 7 Series FPGA User Guide (UG470) 278 * Table 1-1: Bitstream Length 279 * Bits Bytes (sector multiple) 280 * A35T: 17,536,096 0x218000 281 * A100T: 30,606,304 0x3a8000 282 */ 283 reg = <0x00000000 0x218000>; 284 }; 285 }; 286 }; 287 }; 288 }; 289}; 290
