1 /*
2 * Copyright (c) 2023 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #define DT_DRV_COMPAT ite_it8xxx2_gpio_v2
9
10 #include <chip_chipregs.h>
11 #include <errno.h>
12 #include <soc.h>
13 #include <soc_dt.h>
14 #include <string.h>
15 #include <zephyr/device.h>
16 #include <zephyr/drivers/gpio.h>
17 #include <zephyr/drivers/gpio/gpio_utils.h>
18 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
19 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
20 #include <zephyr/init.h>
21 #include <zephyr/irq.h>
22 #include <zephyr/kernel.h>
23 #include <zephyr/spinlock.h>
24 #include <zephyr/sys/util.h>
25 #include <zephyr/types.h>
26 #include <zephyr/logging/log.h>
27
28 LOG_MODULE_REGISTER(gpio_it8xxx2, LOG_LEVEL_ERR);
29
30 /*
31 * Structure gpio_ite_cfg is about the setting of GPIO
32 * this config will be used at initial time
33 */
34 struct gpio_ite_cfg {
35 /* gpio_driver_config needs to be first */
36 struct gpio_driver_config common;
37 /* GPIO port data register (bit mapping to pin) */
38 uintptr_t reg_gpdr;
39 /* GPIO port data mirror register (bit mapping to pin) */
40 uintptr_t reg_gpdmr;
41 /* GPIO port output type register (bit mapping to pin) */
42 uintptr_t reg_gpotr;
43 /* GPIO port 1.8V select register (bit mapping to pin) */
44 uintptr_t reg_p18scr;
45 /* GPIO port control register (byte mapping to pin) */
46 uintptr_t reg_gpcr;
47 /* Wake up control base register */
48 uintptr_t wuc_base[8];
49 /* Wake up control mask */
50 uint8_t wuc_mask[8];
51 /* GPIO's irq */
52 uint8_t gpio_irq[8];
53 /* Support input voltage selection */
54 uint8_t has_volt_sel[8];
55 /* Number of pins per group of GPIO */
56 uint8_t num_pins;
57 /* gpioksi, gpioksoh and gpioksol extended setting */
58 bool kbs_ctrl;
59 };
60
61 /* Structure gpio_ite_data is about callback function */
62 struct gpio_ite_data {
63 struct gpio_driver_data common;
64 sys_slist_t callbacks;
65 uint8_t volt_default_set;
66 struct k_spinlock lock;
67 uint8_t level_isr_high;
68 uint8_t level_isr_low;
69 const struct device *instance;
70 struct k_work interrupt_worker;
71 };
72
73 /**
74 * Driver functions
75 */
gpio_ite_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)76 static int gpio_ite_configure(const struct device *dev,
77 gpio_pin_t pin,
78 gpio_flags_t flags)
79 {
80 const struct gpio_ite_cfg *gpio_config = dev->config;
81 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
82 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
83 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
84 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
85 struct gpio_ite_data *data = dev->data;
86 uint8_t mask = BIT(pin);
87 int rc = 0;
88
89 /* Don't support "open source" mode */
90 if (((flags & GPIO_SINGLE_ENDED) != 0) &&
91 ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
92 return -ENOTSUP;
93 }
94
95 k_spinlock_key_t key = k_spin_lock(&data->lock);
96 if (flags == GPIO_DISCONNECTED) {
97 ECREG(reg_gpcr) = GPCR_PORT_PIN_MODE_TRISTATE;
98 /*
99 * Since not all GPIOs can be to configured as tri-state,
100 * prompt error if pin doesn't support the flag.
101 */
102 if (ECREG(reg_gpcr) != GPCR_PORT_PIN_MODE_TRISTATE) {
103 /* Go back to default setting (input) */
104 ECREG(reg_gpcr) = GPCR_PORT_PIN_MODE_INPUT;
105 LOG_ERR("Cannot config the node-gpio@%x, pin=%d as tri-state",
106 (uint32_t)reg_gpdr, pin);
107 rc = -ENOTSUP;
108 goto unlock_and_return;
109 }
110 /*
111 * The following configuration isn't necessary because the pin
112 * was configured as disconnected.
113 */
114 rc = 0;
115 goto unlock_and_return;
116 }
117
118 /*
119 * Select open drain first, so that we don't glitch the signal
120 * when changing the line to an output.
121 */
122 if (flags & GPIO_OPEN_DRAIN) {
123 ECREG(reg_gpotr) |= mask;
124 } else {
125 ECREG(reg_gpotr) &= ~mask;
126 }
127
128 /* 1.8V or 3.3V */
129 if (gpio_config->has_volt_sel[pin]) {
130 gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
131
132 if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
133 __ASSERT(!(flags & GPIO_PULL_UP),
134 "Don't enable internal pullup if 1.8V voltage is used");
135 ECREG(reg_p18scr) |= mask;
136 data->volt_default_set &= ~mask;
137 } else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3) {
138 ECREG(reg_p18scr) &= ~mask;
139 /*
140 * A variable is needed to store the difference between
141 * 3.3V and default so that the flag can be distinguished
142 * between the two in gpio_ite_get_config.
143 */
144 data->volt_default_set &= ~mask;
145 } else if (volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
146 ECREG(reg_p18scr) &= ~mask;
147 data->volt_default_set |= mask;
148 } else {
149 rc = -EINVAL;
150 goto unlock_and_return;
151 }
152 }
153
154 /* If output, set level before changing type to an output. */
155 if (flags & GPIO_OUTPUT) {
156 if (flags & GPIO_OUTPUT_INIT_HIGH) {
157 ECREG(reg_gpdr) |= mask;
158 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
159 ECREG(reg_gpdr) &= ~mask;
160 }
161 }
162
163 /* Set input or output. */
164 if (gpio_config->kbs_ctrl) {
165 /* Handle keyboard scan controller */
166 uint8_t ksxgctrlr = ECREG(reg_gpcr);
167
168 ksxgctrlr |= KSIX_KSOX_KBS_GPIO_MODE;
169 if (flags & GPIO_OUTPUT) {
170 ksxgctrlr |= KSIX_KSOX_GPIO_OUTPUT;
171 } else {
172 ksxgctrlr &= ~KSIX_KSOX_GPIO_OUTPUT;
173 }
174 ECREG(reg_gpcr) = ksxgctrlr;
175 } else {
176 /* Handle regular GPIO controller */
177 if (flags & GPIO_OUTPUT) {
178 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_OUTPUT) &
179 ~GPCR_PORT_PIN_MODE_INPUT;
180 } else {
181 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_INPUT) &
182 ~GPCR_PORT_PIN_MODE_OUTPUT;
183 }
184 }
185
186 /* Handle pullup / pulldown */
187 if (gpio_config->kbs_ctrl) {
188 /* Handle keyboard scan controller */
189 uint8_t ksxgctrlr = ECREG(reg_gpcr);
190
191 if (flags & GPIO_PULL_UP) {
192 ksxgctrlr = (ksxgctrlr | KSIX_KSOX_GPIO_PULLUP) &
193 ~KSIX_KSOX_GPIO_PULLDOWN;
194 } else if (flags & GPIO_PULL_DOWN) {
195 ksxgctrlr = (ksxgctrlr | KSIX_KSOX_GPIO_PULLDOWN) &
196 ~KSIX_KSOX_GPIO_PULLUP;
197 } else {
198 /* No pull up/down */
199 ksxgctrlr &= ~(KSIX_KSOX_GPIO_PULLUP | KSIX_KSOX_GPIO_PULLDOWN);
200 }
201 ECREG(reg_gpcr) = ksxgctrlr;
202 } else {
203 /* Handle regular GPIO controller */
204 if (flags & GPIO_PULL_UP) {
205 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_PULLUP) &
206 ~GPCR_PORT_PIN_MODE_PULLDOWN;
207 } else if (flags & GPIO_PULL_DOWN) {
208 ECREG(reg_gpcr) = (ECREG(reg_gpcr) | GPCR_PORT_PIN_MODE_PULLDOWN) &
209 ~GPCR_PORT_PIN_MODE_PULLUP;
210 } else {
211 /* No pull up/down */
212 ECREG(reg_gpcr) &= ~(GPCR_PORT_PIN_MODE_PULLUP |
213 GPCR_PORT_PIN_MODE_PULLDOWN);
214 }
215 }
216
217 unlock_and_return:
218 k_spin_unlock(&data->lock, key);
219 return rc;
220 }
221
222 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_ite_get_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t * out_flags)223 static int gpio_ite_get_config(const struct device *dev,
224 gpio_pin_t pin,
225 gpio_flags_t *out_flags)
226 {
227 const struct gpio_ite_cfg *gpio_config = dev->config;
228 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
229 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
230 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
231 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
232 struct gpio_ite_data *data = dev->data;
233 uint8_t mask = BIT(pin);
234 gpio_flags_t flags = 0;
235
236 k_spinlock_key_t key = k_spin_lock(&data->lock);
237 /* push-pull or open-drain */
238 if (ECREG(reg_gpotr) & mask) {
239 flags |= GPIO_OPEN_DRAIN;
240 }
241
242 /* 1.8V or 3.3V */
243 if (gpio_config->has_volt_sel[pin]) {
244 if (data->volt_default_set & mask) {
245 flags |= IT8XXX2_GPIO_VOLTAGE_DEFAULT;
246 } else {
247 if (ECREG(reg_p18scr) & mask) {
248 flags |= IT8XXX2_GPIO_VOLTAGE_1P8;
249 } else {
250 flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
251 }
252 }
253 }
254
255 /* set input or output. */
256 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_OUTPUT) {
257 flags |= GPIO_OUTPUT;
258
259 /* set level */
260 if (ECREG(reg_gpdr) & mask) {
261 flags |= GPIO_OUTPUT_HIGH;
262 } else {
263 flags |= GPIO_OUTPUT_LOW;
264 }
265 }
266
267 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_INPUT) {
268 flags |= GPIO_INPUT;
269
270 /* pullup / pulldown */
271 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_PULLUP) {
272 flags |= GPIO_PULL_UP;
273 }
274
275 if (ECREG(reg_gpcr) & GPCR_PORT_PIN_MODE_PULLDOWN) {
276 flags |= GPIO_PULL_DOWN;
277 }
278 }
279
280 *out_flags = flags;
281 k_spin_unlock(&data->lock, key);
282
283 return 0;
284 }
285 #endif
286
gpio_ite_port_get_raw(const struct device * dev,gpio_port_value_t * value)287 static int gpio_ite_port_get_raw(const struct device *dev,
288 gpio_port_value_t *value)
289 {
290 const struct gpio_ite_cfg *gpio_config = dev->config;
291 volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;
292
293 /* Get raw bits of GPIO mirror register */
294 *value = ECREG(reg_gpdmr);
295
296 return 0;
297 }
298
gpio_ite_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)299 static int gpio_ite_port_set_masked_raw(const struct device *dev,
300 gpio_port_pins_t mask,
301 gpio_port_value_t value)
302 {
303 const struct gpio_ite_cfg *gpio_config = dev->config;
304 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
305 uint8_t masked_value = value & mask;
306 struct gpio_ite_data *data = dev->data;
307 k_spinlock_key_t key = k_spin_lock(&data->lock);
308 uint8_t out = ECREG(reg_gpdr);
309
310 ECREG(reg_gpdr) = ((out & ~mask) | masked_value);
311 k_spin_unlock(&data->lock, key);
312
313 return 0;
314 }
315
gpio_ite_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)316 static int gpio_ite_port_set_bits_raw(const struct device *dev,
317 gpio_port_pins_t pins)
318 {
319 const struct gpio_ite_cfg *gpio_config = dev->config;
320 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
321 struct gpio_ite_data *data = dev->data;
322
323 k_spinlock_key_t key = k_spin_lock(&data->lock);
324 /* Set raw bits of GPIO data register */
325 ECREG(reg_gpdr) |= pins;
326 k_spin_unlock(&data->lock, key);
327
328 return 0;
329 }
330
gpio_ite_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)331 static int gpio_ite_port_clear_bits_raw(const struct device *dev,
332 gpio_port_pins_t pins)
333 {
334 const struct gpio_ite_cfg *gpio_config = dev->config;
335 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
336 struct gpio_ite_data *data = dev->data;
337
338 k_spinlock_key_t key = k_spin_lock(&data->lock);
339 /* Clear raw bits of GPIO data register */
340 ECREG(reg_gpdr) &= ~pins;
341 k_spin_unlock(&data->lock, key);
342
343 return 0;
344 }
345
gpio_ite_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)346 static int gpio_ite_port_toggle_bits(const struct device *dev,
347 gpio_port_pins_t pins)
348 {
349 const struct gpio_ite_cfg *gpio_config = dev->config;
350 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
351 struct gpio_ite_data *data = dev->data;
352
353 k_spinlock_key_t key = k_spin_lock(&data->lock);
354 /* Toggle raw bits of GPIO data register */
355 ECREG(reg_gpdr) ^= pins;
356 k_spin_unlock(&data->lock, key);
357
358 return 0;
359 }
360
gpio_ite_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)361 static int gpio_ite_manage_callback(const struct device *dev,
362 struct gpio_callback *callback,
363 bool set)
364 {
365 struct gpio_ite_data *data = dev->data;
366
367 k_spinlock_key_t key = k_spin_lock(&data->lock);
368 int rc = gpio_manage_callback(&data->callbacks, callback, set);
369
370 k_spin_unlock(&data->lock, key);
371 return rc;
372 }
373
gpio_ite_isr(const void * arg)374 static void gpio_ite_isr(const void *arg)
375 {
376 const struct device *dev = arg;
377 const struct gpio_ite_cfg *gpio_config = dev->config;
378 struct gpio_ite_data *data = dev->data;
379 uint8_t irq = ite_intc_get_irq_num();
380 uint8_t num_pins = gpio_config->num_pins;
381 uint8_t pin;
382
383 for (pin = 0; pin < num_pins; pin++) {
384 if (irq == gpio_config->gpio_irq[pin]) {
385 volatile uint8_t *reg_base =
386 (uint8_t *)gpio_config->wuc_base[pin];
387 volatile uint8_t *reg_wuesr = reg_base + 1;
388 uint8_t wuc_mask = gpio_config->wuc_mask[pin];
389
390 /* Should be safe even without spinlock. */
391 /* Clear the WUC status register. */
392 ECREG(reg_wuesr) = wuc_mask;
393 /* The callbacks are user code, and therefore should
394 * not hold the lock.
395 */
396 gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
397
398 break;
399 }
400 }
401 /* Reschedule worker */
402 k_work_submit(&data->interrupt_worker);
403 }
404
gpio_ite_interrupt_worker(struct k_work * work)405 static void gpio_ite_interrupt_worker(struct k_work *work)
406 {
407 struct gpio_ite_data * const data = CONTAINER_OF(
408 work, struct gpio_ite_data, interrupt_worker);
409 gpio_port_value_t value;
410 gpio_port_value_t triggered_int;
411
412 gpio_ite_port_get_raw(data->instance, &value);
413
414 k_spinlock_key_t key = k_spin_lock(&data->lock);
415
416 triggered_int = (value & data->level_isr_high) | (~value & data->level_isr_low);
417 k_spin_unlock(&data->lock, key);
418
419 if (triggered_int != 0) {
420 gpio_fire_callbacks(&data->callbacks, data->instance,
421 triggered_int);
422 /* Reschedule worker */
423 k_work_submit(&data->interrupt_worker);
424 }
425 }
426
gpio_ite_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)427 static int gpio_ite_pin_interrupt_configure(const struct device *dev,
428 gpio_pin_t pin,
429 enum gpio_int_mode mode,
430 enum gpio_int_trig trig)
431 {
432 const struct gpio_ite_cfg *gpio_config = dev->config;
433 uint8_t gpio_irq = gpio_config->gpio_irq[pin];
434 struct gpio_ite_data *data = dev->data;
435
436 #ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
437 if (mode == GPIO_INT_MODE_DISABLED || mode == GPIO_INT_MODE_DISABLE_ONLY) {
438 #else
439 if (mode == GPIO_INT_MODE_DISABLED) {
440 #endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
441 /* Disable GPIO interrupt */
442 irq_disable(gpio_irq);
443 return 0;
444 #ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
445 } else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
446 /* Only enable GPIO interrupt */
447 irq_enable(gpio_irq);
448 return 0;
449 #endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
450 }
451
452 /* Disable irq before configuring it */
453 irq_disable(gpio_irq);
454
455 if (trig & GPIO_INT_TRIG_BOTH) {
456 volatile uint8_t *reg_base = (uint8_t *)gpio_config->wuc_base[pin];
457 volatile uint8_t *reg_wuemr = reg_base;
458 volatile uint8_t *reg_wuesr = reg_base + 1;
459 volatile uint8_t *reg_wubemr = reg_base + 3;
460 uint8_t wuc_mask = gpio_config->wuc_mask[pin];
461
462 k_spinlock_key_t key = k_spin_lock(&data->lock);
463
464 /* Set both edges interrupt. */
465 if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
466 ECREG(reg_wubemr) |= wuc_mask;
467 } else {
468 ECREG(reg_wubemr) &= ~wuc_mask;
469 }
470
471 if (trig & GPIO_INT_TRIG_LOW) {
472 ECREG(reg_wuemr) |= wuc_mask;
473 } else {
474 ECREG(reg_wuemr) &= ~wuc_mask;
475 }
476
477 if (mode == GPIO_INT_MODE_LEVEL) {
478 if (trig & GPIO_INT_TRIG_LOW) {
479 data->level_isr_low |= BIT(pin);
480 data->level_isr_high &= ~BIT(pin);
481 } else {
482 data->level_isr_low &= ~BIT(pin);
483 data->level_isr_high |= BIT(pin);
484 }
485 } else {
486 data->level_isr_low &= ~BIT(pin);
487 data->level_isr_high &= ~BIT(pin);
488 }
489 /*
490 * Always write 1 to clear the WUC status register after
491 * modifying edge mode selection register (WUBEMR and WUEMR).
492 */
493 ECREG(reg_wuesr) = wuc_mask;
494 k_spin_unlock(&data->lock, key);
495 }
496
497 /* Enable GPIO interrupt */
498 irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
499 irq_enable(gpio_irq);
500 k_work_submit(&data->interrupt_worker);
501
502 return 0;
503 }
504
505 static DEVICE_API(gpio, gpio_ite_driver_api) = {
506 .pin_configure = gpio_ite_configure,
507 #ifdef CONFIG_GPIO_GET_CONFIG
508 .pin_get_config = gpio_ite_get_config,
509 #endif
510 .port_get_raw = gpio_ite_port_get_raw,
511 .port_set_masked_raw = gpio_ite_port_set_masked_raw,
512 .port_set_bits_raw = gpio_ite_port_set_bits_raw,
513 .port_clear_bits_raw = gpio_ite_port_clear_bits_raw,
514 .port_toggle_bits = gpio_ite_port_toggle_bits,
515 .pin_interrupt_configure = gpio_ite_pin_interrupt_configure,
516 .manage_callback = gpio_ite_manage_callback,
517 };
518
519 static int gpio_ite_init(const struct device *dev)
520 {
521 struct gpio_ite_data *data = dev->data;
522 k_spinlock_key_t key = k_spin_lock(&data->lock);
523
524 data->instance = dev;
525 k_work_init(&data->interrupt_worker,
526 gpio_ite_interrupt_worker);
527 k_spin_unlock(&data->lock, key);
528
529 return 0;
530 }
531
532 #define GPIO_ITE_DEV_CFG_DATA(inst) \
533 static struct gpio_ite_data gpio_ite_data_##inst; \
534 static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
535 .common = { \
536 .port_pin_mask = \
537 GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) \
538 }, \
539 .reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
540 .reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
541 .reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
542 .reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
543 .reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4), \
544 .wuc_base = DT_INST_PROP_OR(inst, wuc_base, {0}), \
545 .wuc_mask = DT_INST_PROP_OR(inst, wuc_mask, {0}), \
546 .gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst), \
547 .has_volt_sel = DT_INST_PROP_OR(inst, has_volt_sel, {0}), \
548 .num_pins = DT_INST_PROP(inst, ngpios), \
549 .kbs_ctrl = DT_INST_PROP_OR(inst, keyboard_controller, 0), \
550 }; \
551 DEVICE_DT_INST_DEFINE(inst, \
552 gpio_ite_init, \
553 NULL, \
554 &gpio_ite_data_##inst, \
555 &gpio_ite_cfg_##inst, \
556 PRE_KERNEL_1, \
557 CONFIG_GPIO_INIT_PRIORITY, \
558 &gpio_ite_driver_api);
559
560 DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
561
562 #ifdef CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
563 static int gpio_it8xxx2_init_set(void)
564 {
565 const struct device *const gpiok = DEVICE_DT_GET(DT_NODELABEL(gpiok));
566 const struct device *const gpiol = DEVICE_DT_GET(DT_NODELABEL(gpiol));
567
568 for (int i = 0; i < 8; i++) {
569 gpio_pin_configure(gpiok, i, GPIO_INPUT | GPIO_PULL_DOWN);
570 gpio_pin_configure(gpiol, i, GPIO_INPUT | GPIO_PULL_DOWN);
571 }
572
573 return 0;
574 }
575 SYS_INIT(gpio_it8xxx2_init_set, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY);
576 #endif /* CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN */
577
