Lines Matching +full:tri +full:- +full:default

2 # SPDX-License-Identifier: Apache-2.0
5 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
6 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
9   Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and
18   #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
21     pinctrl_uart1_default: uart1-default {
29         slew-rate = <IO_SPEED_SLOW>;
30         power-source = <IO_STANDARD_LVCMOS18>;
33       conf-rx {
35         bias-high-impedance;
38       conf-tx {
40         bias-disable;
45   See the Xilinx Zynq-7000 SoC Technical Reference Manual (UG585) for further details on pin
48 compatible: "xlnx,pinctrl-zynq"
64 child-binding:
68   child-binding:
73       - name: pincfg-node.yaml
74         property-allowlist:
75           - bias-disable
76           - bias-high-impedance
77           - bias-pull-up
78           - low-power-enable
79           - low-power-disable
80           - power-source
81           - slew-rate
85         type: string-array
126         type: string-array
146       bias-disable:
151       bias-high-impedance:
153           Enables tri-state on IO buffer pin. Sets the TRI_ENABLE field in the MIO_PIN_xx SLCR
156       bias-pull-up:
158           Enables pull-up on IO buffer pin. Sets the PULLUP field in the MIO_PIN_xx SLCR register.
160       low-power-enable:
162           Disable HSTL input buffer to save power when it is an output-only. Applicable when
163           power-source (IO_Type) is HSTL. Sets the DisableRcvr field in the MIO_PIN_xx SLCR
166       low-power-disable:
168           Enable HSTL input buffer. Applicable when the power-souce (IO_Type) is HSTL. Clears the
171       power-source:
175           macros are defined in pinctrl-zynq.h.
182       slew-rate:
185           IO buffer edge rate. Applicable when the power-source (IO_type) is LVCMOS18, LVCMOS25, or
187           defined in pinctrl-zynq.h.