4  * SPDX-License-Identifier: Apache-2.0
53 	 * KSO push-pull/open-drain bit of KSO[15:0] control register
74 	const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;  in pinctrl_it8xxx2_set()
75 	const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);  in pinctrl_it8xxx2_set()
76 	uint32_t pincfg = pins->pincfg;  in pinctrl_it8xxx2_set()
77 	uint8_t pin = pins->pin;  in pinctrl_it8xxx2_set()
78 	volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;  in pinctrl_it8xxx2_set()
79 	volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]);  in pinctrl_it8xxx2_set()
80 	volatile uint8_t *reg_pdsc = (uint8_t *)gpio->reg_pdsc;  in pinctrl_it8xxx2_set()
82 	/* Setting pull-up or pull-down. */  in pinctrl_it8xxx2_set()
85 		/* No pull-up or pull-down */  in pinctrl_it8xxx2_set()
97 	default:  in pinctrl_it8xxx2_set()
99 		return -EINVAL;  in pinctrl_it8xxx2_set()
111 			*reg_volt_sel &= ~gpio->volt_sel_mask[pin];  in pinctrl_it8xxx2_set()
118 			*reg_volt_sel |= gpio->volt_sel_mask[pin];  in pinctrl_it8xxx2_set()
120 		default:  in pinctrl_it8xxx2_set()
122 			return -EINVAL;  in pinctrl_it8xxx2_set()
126 	/* Setting tri-state mode. */  in pinctrl_it8xxx2_set()
149 	const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;  in pinctrl_gpio_it8xxx2_configure_pins()
150 	const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio);  in pinctrl_gpio_it8xxx2_configure_pins()
151 	uint8_t pin = pins->pin;  in pinctrl_gpio_it8xxx2_configure_pins()
152 	volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;  in pinctrl_gpio_it8xxx2_configure_pins()
153 	volatile uint8_t *reg_func3_gcr = (uint8_t *)(gpio->func3_gcr[pin]);  in pinctrl_gpio_it8xxx2_configure_pins()
154 	volatile uint8_t *reg_func4_gcr = (uint8_t *)(gpio->func4_gcr[pin]);  in pinctrl_gpio_it8xxx2_configure_pins()
155 	volatile uint8_t *reg_func3_ext = (uint8_t *)(gpio->func3_ext[pin]);  in pinctrl_gpio_it8xxx2_configure_pins()
160 		return -EINVAL;  in pinctrl_gpio_it8xxx2_configure_pins()
164 	 * Default input mode prevents leakage during changes to extended  in pinctrl_gpio_it8xxx2_configure_pins()
174 	if (IT8XXX2_DT_PINCFG_INPUT(pins->pincfg)) {  in pinctrl_gpio_it8xxx2_configure_pins()
182 		*reg_func3_gcr &= ~gpio->func3_en_mask[pin];  in pinctrl_gpio_it8xxx2_configure_pins()
184 	/* Ensure that func3-ext setting is in default state. */  in pinctrl_gpio_it8xxx2_configure_pins()
186 		*reg_func3_ext &= ~gpio->func3_ext_mask[pin];  in pinctrl_gpio_it8xxx2_configure_pins()
189 	switch (pins->alt_func) {  in pinctrl_gpio_it8xxx2_configure_pins()
202 			*reg_func3_gcr |= gpio->func3_en_mask[pin];  in pinctrl_gpio_it8xxx2_configure_pins()
204 		/* Func3-external: Some pins require external setting. */  in pinctrl_gpio_it8xxx2_configure_pins()
206 			*reg_func3_ext |= gpio->func3_ext_mask[pin];  in pinctrl_gpio_it8xxx2_configure_pins()
214 		*reg_func4_gcr |= gpio->func4_en_mask[pin];  in pinctrl_gpio_it8xxx2_configure_pins()
217 		*reg_func3_gcr &= ~gpio->func3_en_mask[pin];  in pinctrl_gpio_it8xxx2_configure_pins()
218 		*reg_func4_gcr &= ~gpio->func4_en_mask[pin];  in pinctrl_gpio_it8xxx2_configure_pins()
220 	default:  in pinctrl_gpio_it8xxx2_configure_pins()
222 		return -EINVAL;  in pinctrl_gpio_it8xxx2_configure_pins()
234 	const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;  in pinctrl_kscan_it8xxx2_set()
235 	const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);  in pinctrl_kscan_it8xxx2_set()
236 	volatile uint8_t *reg_ctrl = ksi_kso->reg_ctrl;  in pinctrl_kscan_it8xxx2_set()
237 	uint8_t pullup_mask = ksi_kso->pullup_mask;  in pinctrl_kscan_it8xxx2_set()
238 	uint8_t pp_od_mask = ksi_kso->pp_od_mask;  in pinctrl_kscan_it8xxx2_set()
239 	uint32_t pincfg = pins->pincfg;  in pinctrl_kscan_it8xxx2_set()
242 	 * Enable or disable internal pull-up (this bit apply to all pins):  in pinctrl_kscan_it8xxx2_set()
244 	 * pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).  in pinctrl_kscan_it8xxx2_set()
249 		/* Disable internal pulll-up */  in pinctrl_kscan_it8xxx2_set()
255 	default:  in pinctrl_kscan_it8xxx2_set()
257 		return -EINVAL;  in pinctrl_kscan_it8xxx2_set()
261 	 * Set push-pull or open-drain mode (this bit apply to all pins):  in pinctrl_kscan_it8xxx2_set()
262 	 * KSI[7:0] doesn't support push-pull and open-drain settings in kbs mode.  in pinctrl_kscan_it8xxx2_set()
263 	 * If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,  in pinctrl_kscan_it8xxx2_set()
264 	 * setting 0 selects push-pull mode.  in pinctrl_kscan_it8xxx2_set()
275 		default:  in pinctrl_kscan_it8xxx2_set()
277 			return -EINVAL;  in pinctrl_kscan_it8xxx2_set()
286 	const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config;
287 	const struct pinctrl_it8xxx2_ksi_kso *ksi_kso = &(pinctrl_config->ksi_kso);
289 	/* Set a pin of KSI[7:0]/KSO[15:0] to pullup, push-pull/open-drain */
291 		return -EINVAL;
295 	uint8_t pin_mask = BIT(pins->pin);
296 	volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl;
298 	switch (pins->alt_func) {
308 	uint8_t pin = pins->pin;
309 	volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl + pin;
311 	switch (pins->alt_func) {
323 	default:
325 		return -ENOTSUP;
339 		pinctrl_config = pins[i].pinctrls->config;
341 		if (pinctrl_config->gpio_group) {
349 				pins[i].pinctrls->name, pins[i].pin);
362 	 * The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
366 	gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
375 	 * GCR7 or func3-ext of GPIO extended, it will cause leakage.
384 	 * Swap the default I2C2 SMCLK2/SMDAT2 pins from GPC7/GPD0 to GPF6/GPF7,
388 	gpio_base->GPIO_GCR7 &= ~(IT8XXX2_GPIO_SMB2PS |