Searched +full:clock +full:- +full:type (Results 1 – 25 of 783) sorted by relevance
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| /Zephyr-latest/dts/bindings/clock/ |
| D | litex,clkout.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 LiteX Mixed Mode Clock Manager clock output binding
13 "#clock-cells":
15 type: int
17 Number of cells in a clock specifier;
18 Typically 0 for nodes with a single clock output
19 and 1 for nodes with multiple clock outputs.
22 clock-output-names:
24 type: string
26 string of clock output signal name.
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| D | microchip,xec-pcr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
15 type: int
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
20 type: int
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
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| D | intel,adsp-shim-clkctl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Intel ADSP clock controlling related constants.
6 compatible: "intel,adsp-shim-clkctl"
9 adsp-clkctl-clk-wovcro:
10 type: int
12 Index of WOVCRO clock encoding in the encoding array (if wovcro-supported is true).
14 adsp-clkctl-clk-lpro:
15 type: int
16 description: Index of LPRO clock encoding in the encoding array.
18 adsp-clkctl-clk-hpro:
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| D | litex,clk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
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| D | st,stm32g0-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 It can take one of clk_hse or clk_hsi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
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| D | fixed-factor-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Generic fixed factor clock provider
6 compatible: "fixed-factor-clock"
8 include: clock-controller.yaml
11 clock-div:
12 type: int
13 description: fixed clock divider
15 clock-mult:
16 type: int
17 description: fixed clock multiplier
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| D | st,stm32h7-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7 devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
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| D | st,stm32u5-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
11 clock in this acceptable range.
13 Each PLL can have up to 3 output clocks and for each output clock, the
16 f(PLL_P) = f(VCO clock) / PLLP
17 f(PLL_Q) = f(VCO clock) / PLLQ
18 f(PLL_R) = f(VCO clock) / PLLR
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 clock output to the lowest frequency.
27 compatible: "st,stm32u5-pll-clock"
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| D | st,stm32u0-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32u0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
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| D | st,stm32h7-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
18 f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
19 f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
21 with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
25 compatible: "st,stm32h7-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
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| D | st,stm32h7rs-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7RS devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7rs-rcc"
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| D | st,stm32wba-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
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| D | st,stm32wb-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLPCLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
24 - 64 MHz on STM32WB
25 - 62 MHz on STM32WL
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| D | st,stm32f4-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse or clk_hsi as input clock, with an
8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
11 Up to 2 output clocks could be supported and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32f4-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
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| D | atmel,sam-pmc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 the clock inputs to many of the peripherals and the processor.
16 clocks = <&pmc PMC_TYPE_PERIPHERAL p-id>;
20 In this example the clock-type was defined as PMC_TYPE_PERIPHERAL and the
21 peripheral-id was defined as p-id. The p-id number should be consulted on
24 NOTE: The predefined clock type cell is defined at
27 The clock-type constants are:
34 compatible: "atmel,sam-pmc"
36 include: [clock-controller.yaml, base.yaml]
42 "#clock-cells":
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| D | st,stm32l4-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
25 compatible: "st,stm32l4-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
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| D | nxp,kinetis-sim.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-sim"
14 pllfll-select:
15 type: int
17 description: pll/fll selection for clock system
19 er32k-select:
20 type: int
22 description: er32k selection for clock system
24 clkout-source:
25 type: int
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| D | st,stm32f7-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse or clk_hsi as input clock.
9 Up to 2 output clocks could be supported and for each output clock, the
12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18 compatible: "st,stm32f7-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23 "#clock-cells":
29 div-m:
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| D | st,stm32f2-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse or clk_hsi as input clock.
9 Up to 2 output clocks could be supported and for each output clock, the
12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
20 compatible: "st,stm32f2-pll-clock"
22 include: [clock-controller.yaml, base.yaml]
25 "#clock-cells":
31 div-m:
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| /Zephyr-latest/dts/bindings/usb/uac2/ |
| D | zephyr,uac2-clock-source.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: USB Audio Class 2 Clock Source entity
6 compatible: "zephyr,uac2-clock-source"
9 clock-type:
10 type: string
13 Clock Type indicating whether the Clock Source represents an external
14 clock or an internal clock with either fixed frequency, variable
17 - "external"
18 - "internal-fixed"
19 - "internal-variable"
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | telink,b91-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
9 compatible: "telink,b91-pwm"
13 pinctrl-0:
16 clock-frequency:
17 type: int
19 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
21 clk32k-ch0-enable:
22 type: boolean
23 description: Enable 32K Source Clock for PWM Channel 0
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| D | microchip,xec-pwmbbled.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
18 type: array
23 type: array
27 clock-select:
28 type: string
31 Clock source selection: 32 KHz is available in deep sleep.
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
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| /Zephyr-latest/dts/bindings/i2s/ |
| D | nxp,mcux-i2s.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP mcux SAI-I2S controller
6 compatible: "nxp,mcux-i2s"
8 include: [i2s-controller.yaml, pinctrl-device.yaml]
17 dma-names:
20 nxp,tx-dma-channel:
21 type: int
25 nxp,rx-dma-channel:
26 type: int
30 nxp,tx-sync-mode:
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| /Zephyr-latest/dts/bindings/adc/ |
| D | adi,max32-adc.yaml | 1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 channel-count:
27 type: int
31 vref-mv:
32 type: int
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| D | st,stm32-adc.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "st,stm32-adc"
9 include: [adc-controller.yaml, pinctrl-device.yaml]
21 "#io-channel-cells":
24 st,adc-clock-source:
25 type: string
28 - "SYNC"
29 - "ASYNC"
31 Type of ADC clock source :
32 - "SYNC": derived from the bus clock.
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