1# Copyright (c) 2023-2024 Analog Devices, Inc.
2# SPDX-License-Identifier: Apache-2.0
3
4description: ADI MAX32 ADC
5
6compatible: "adi,max32-adc"
7
8include: [adc-controller.yaml, pinctrl-device.yaml]
9
10properties:
11  reg:
12    required: true
13
14  interrupts:
15    required: true
16
17  clocks:
18    required: true
19
20  pinctrl-0:
21    required: true
22
23  pinctrl-names:
24    required: true
25
26  channel-count:
27    type: int
28    required: true
29    description: The maximum channels supported on each unit.
30
31  vref-mv:
32    type: int
33    required: true
34    description: Indicates the reference voltage of the ADC in mV (on the target board).
35
36  resolution:
37    type: int
38    required: true
39    description: Indicates the resolution supported by the ADC instance.
40
41  clock-source:
42    required: true
43    type: int
44    enum: [0, 1, 2, 3]
45    description: |
46      Clock source to be used by the ADC peripheral. The following options
47      are available:
48      - 0: "ADI_MAX32_PRPH_CLK_SRC_PCLK" Peripheral clock
49      - 1: "ADI_MAX32_PRPH_CLK_SRC_EXTCLK" External Clock
50      - 2: "ADI_MAX32_PRPH_CLK_SRC_IBRO" Internal Baud Rate Oscillator
51      - 3: "ADI_MAX32_PRPH_CLK_SRC_ERFO" External Radio Frequency Oscillator
52      The target device might not support every option please take a look on
53      target device user guide
54
55  clock-divider:
56    required: true
57    type: int
58    enum: [1, 2, 4, 8, 16]
59    description: |
60      The clock divider divides the ADC source clock to set the ADC clock frequency as follows:
61        F_sar_clk = F_clock_source / clock divider
62
63  track-count:
64    required: true
65    type: int
66    description: |
67      The number of cycles to add to the minimum track time.
68
69  idle-count:
70    required: true
71    type: int
72    description: |
73      The number of cycles to add to the minimum hold time.
74
75  "#io-channel-cells":
76    const: 1
77
78io-channel-cells:
79  - input
80