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Searched full:cctl (Results 1 – 19 of 19) sorted by relevance

/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi44 cctl: clock-controller { label
45 compatible = "gd,gd32-cctl";
75 clocks = <&cctl GD32_CLOCK_USART0>;
84 clocks = <&cctl GD32_CLOCK_USART1>;
93 clocks = <&cctl GD32_CLOCK_USART2>;
102 clocks = <&cctl GD32_CLOCK_UART3>;
111 clocks = <&cctl GD32_CLOCK_UART4>;
120 clocks = <&cctl GD32_CLOCK_USART5>;
129 clocks = <&cctl GD32_CLOCK_UART6>;
138 clocks = <&cctl GD32_CLOCK_UART7>;
[all …]
Dgd32f450.dtsi16 clocks = <&cctl GD32_CLOCK_SPI3>;
27 clocks = <&cctl GD32_CLOCK_SPI4>;
38 clocks = <&cctl GD32_CLOCK_SPI5>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi45 cctl: clock-controller { label
46 compatible = "gd,gd32-cctl";
77 clocks = <&cctl GD32_CLOCK_USART0>;
86 clocks = <&cctl GD32_CLOCK_USART1>;
95 clocks = <&cctl GD32_CLOCK_USART2>;
104 clocks = <&cctl GD32_CLOCK_UART3>;
113 clocks = <&cctl GD32_CLOCK_UART4>;
122 clocks = <&cctl GD32_CLOCK_SPI0>;
133 clocks = <&cctl GD32_CLOCK_SPI1>;
144 clocks = <&cctl GD32_CLOCK_SPI2>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi39 cctl: clock-controller { label
40 compatible = "gd,gd32-cctl";
70 clocks = <&cctl GD32_CLOCK_USART0>;
79 clocks = <&cctl GD32_CLOCK_USART1>;
88 clocks = <&cctl GD32_CLOCK_USART2>;
97 clocks = <&cctl GD32_CLOCK_UART3>;
106 clocks = <&cctl GD32_CLOCK_UART4>;
114 clocks = <&cctl GD32_CLOCK_DAC>;
129 clocks = <&cctl GD32_CLOCK_I2C0>;
142 clocks = <&cctl GD32_CLOCK_I2C1>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi39 cctl: clock-controller { label
40 compatible = "gd,gd32-cctl";
83 clocks = <&cctl GD32_CLOCK_USART0>;
92 clocks = <&cctl GD32_CLOCK_USART1>;
101 clocks = <&cctl GD32_CLOCK_USART2>;
110 clocks = <&cctl GD32_CLOCK_UART3>;
119 clocks = <&cctl GD32_CLOCK_UART4>;
129 clocks = <&cctl GD32_CLOCK_USART5>;
137 clocks = <&cctl GD32_CLOCK_DAC>;
152 clocks = <&cctl GD32_CLOCK_I2C0>;
[all …]
Dgd32e507xe.dtsi17 clocks = <&cctl GD32_CLOCK_TIMER7>;
35 clocks = <&cctl GD32_CLOCK_TIMER8>;
52 clocks = <&cctl GD32_CLOCK_TIMER9>;
69 clocks = <&cctl GD32_CLOCK_TIMER10>;
86 clocks = <&cctl GD32_CLOCK_TIMER11>;
103 clocks = <&cctl GD32_CLOCK_TIMER12>;
120 clocks = <&cctl GD32_CLOCK_TIMER13>;
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi45 cctl: clock-controller { label
46 compatible = "gd,gd32-cctl";
78 clocks = <&cctl GD32_CLOCK_USART0>;
87 clocks = <&cctl GD32_CLOCK_USART1>;
96 clocks = <&cctl GD32_CLOCK_USART2>;
104 clocks = <&cctl GD32_CLOCK_DAC>;
119 clocks = <&cctl GD32_CLOCK_I2C0>;
132 clocks = <&cctl GD32_CLOCK_I2C1>;
141 clocks = <&cctl GD32_CLOCK_SPI0>;
152 clocks = <&cctl GD32_CLOCK_SPI1>;
[all …]
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi66 cctl: clock-controller { label
67 compatible = "gd,gd32-cctl";
97 clocks = <&cctl GD32_CLOCK_USART0>;
106 clocks = <&cctl GD32_CLOCK_USART1>;
115 clocks = <&cctl GD32_CLOCK_USART2>;
124 clocks = <&cctl GD32_CLOCK_UART3>;
133 clocks = <&cctl GD32_CLOCK_UART4>;
142 clocks = <&cctl GD32_CLOCK_ADC0>;
153 clocks = <&cctl GD32_CLOCK_ADC1>;
163 clocks = <&cctl GD32_CLOCK_DAC>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi37 cctl: clock-controller { label
38 compatible = "gd,gd32-cctl";
69 clocks = <&cctl GD32_CLOCK_USART0>;
78 clocks = <&cctl GD32_CLOCK_USART1>;
88 clocks = <&cctl GD32_CLOCK_ADC>;
99 clocks = <&cctl GD32_CLOCK_DMA>;
114 clocks = <&cctl GD32_CLOCK_WWDGT>;
132 clocks = <&cctl GD32_CLOCK_GPIOA>;
142 clocks = <&cctl GD32_CLOCK_GPIOB>;
152 clocks = <&cctl GD32_CLOCK_GPIOC>;
[all …]
Dgd32f350.dtsi15 clocks = <&cctl GD32_CLOCK_DAC>;
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l23x.dtsi37 cctl: clock-controller { label
38 compatible = "gd,gd32-cctl";
53 clocks = <&cctl GD32_CLOCK_SYSCFG>;
73 clocks = <&cctl GD32_CLOCK_USART0>;
82 clocks = <&cctl GD32_CLOCK_USART1>;
91 clocks = <&cctl GD32_CLOCK_UART3>;
100 clocks = <&cctl GD32_CLOCK_ADC>;
132 clocks = <&cctl GD32_CLOCK_GPIOA>;
142 clocks = <&cctl GD32_CLOCK_GPIOB>;
152 clocks = <&cctl GD32_CLOCK_GPIOC>;
[all …]
Dgd32l233rc.dtsi27 clocks = <&cctl GD32_CLOCK_UART4>;
/Zephyr-latest/dts/bindings/clock/
Dgd,gd32-cctl.yaml6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
7 peripherals. This binding represents the clock controller (CCTL).
15 clocks = <&cctl GD32_CLOCK_GPIOA>;
23 compatible: "gd,gd32-cctl"
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dgd32.h15 * There is a single clock controller in the GD32: cctl. The device can be
19 #define GD32_CLOCK_CONTROLLER DEVICE_DT_GET(DT_NODELABEL(cctl))
/Zephyr-latest/drivers/cache/
Dcache_andes_l2.h36 /* L2 cache CCTL Access Line registers bitfields */
39 /* L2 CCTL Command */
121 /* Wait L2 CCTL Commands finished */ in nds_l2_cache_all()
137 /* Wait L2 CCTL Commands finished */ in nds_l2_cache_all()
178 /* Wait L2 CCTL Commands finished */ in nds_l2_cache_range()
Dcache_andes.c17 /* L1 CCTL Command */
341 /* CCTL IX type command is not to RISC-V Smepmp */ in cache_instr_invd_all()
/Zephyr-latest/dts/bindings/mfd/
Dgd,gd32-rcu.yaml6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
/Zephyr-latest/dts/bindings/reset/
Dgd,gd32-rctl.yaml6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst1079 * :dtcompatible:`gd,gd32-cctl`
1211 :dtcompatible:`gd,gd32-cctl` clock controller binding: