1/*
2 * Copyright (c) 2022 BrainCo Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <gd/gd32l23x/gd32l23x.dtsi>
9
10/ {
11	soc {
12		sram1: memory@20004000 {
13			compatible = "mmio-sram";
14			reg = <0x20004000 DT_SIZE_K(16)>;
15		};
16
17		/* Combine SRAM0(16K) and SRAM1(16K), since its address is continuous. */
18		sram: memory@20000000 {
19			compatible = "mmio-sram";
20			reg = <0x20000000 DT_SIZE_K(32)>;
21		};
22
23		uart4: usart@40005000 {
24			compatible = "gd,gd32-usart";
25			reg = <0x40005000 0x400>;
26			interrupts = <30 0>;
27			clocks = <&cctl GD32_CLOCK_UART4>;
28			resets = <&rctl GD32_RESET_UART4>;
29			status = "disabled";
30		};
31	};
32};
33
34&flash0 {
35	reg = <0x08000000 DT_SIZE_K(256)>;
36	/* GD32L23X DataSheet not defined the maximum page erase time
37	 * for flash memory.
38	 * From other GD32 DataSheets, we can find 1KB page normally have a
39	 * 300ms max time.
40	 * Assume GD32L23X use the worst implementation, set the max erase
41	 * time to 4 times of 1KB page.
42	 */
43	max-erase-time-ms = <1200>;
44	page-size = <DT_SIZE_K(4)>;
45};
46