Lines Matching full:cctl
66 cctl: clock-controller { label
67 compatible = "gd,gd32-cctl";
97 clocks = <&cctl GD32_CLOCK_USART0>;
106 clocks = <&cctl GD32_CLOCK_USART1>;
115 clocks = <&cctl GD32_CLOCK_USART2>;
124 clocks = <&cctl GD32_CLOCK_UART3>;
133 clocks = <&cctl GD32_CLOCK_UART4>;
142 clocks = <&cctl GD32_CLOCK_ADC0>;
153 clocks = <&cctl GD32_CLOCK_ADC1>;
163 clocks = <&cctl GD32_CLOCK_DAC>;
178 clocks = <&cctl GD32_CLOCK_I2C0>;
187 clocks = <&cctl GD32_CLOCK_SPI0>;
198 clocks = <&cctl GD32_CLOCK_SPI1>;
208 clocks = <&cctl GD32_CLOCK_AFIO>;
235 clocks = <&cctl GD32_CLOCK_WWDGT>;
253 clocks = <&cctl GD32_CLOCK_GPIOA>;
263 clocks = <&cctl GD32_CLOCK_GPIOB>;
273 clocks = <&cctl GD32_CLOCK_GPIOC>;
283 clocks = <&cctl GD32_CLOCK_GPIOD>;
293 clocks = <&cctl GD32_CLOCK_GPIOE>;
304 clocks = <&cctl GD32_CLOCK_TIMER0>;
322 clocks = <&cctl GD32_CLOCK_TIMER1>;
339 clocks = <&cctl GD32_CLOCK_TIMER2>;
356 clocks = <&cctl GD32_CLOCK_TIMER3>;
373 clocks = <&cctl GD32_CLOCK_TIMER4>;
390 clocks = <&cctl GD32_CLOCK_TIMER5>;
401 clocks = <&cctl GD32_CLOCK_TIMER6>;
412 clocks = <&cctl GD32_CLOCK_DMA0>;
424 clocks = <&cctl GD32_CLOCK_DMA1>;