| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | clock.c | 13 BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 1,
20 * HFXOSC (16 MHz) is used to produce coreclk (and therefore tlclk / in soc_early_init_hook()
22 * - 16 MHz (bypass HFPLL). in soc_early_init_hook()
23 * - 48 MHz - 320 MHz, in 8 MHz steps (use HFPLL). in soc_early_init_hook()
25 BUILD_ASSERT(MHZ(16) == CORECLK_HZ || in soc_early_init_hook()
26 (MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ && in soc_early_init_hook()
27 (CORECLK_HZ % MHZ(8)) == 0), in soc_early_init_hook()
32 if (MHZ(16) == CORECLK_HZ) { in soc_early_init_hook()
34 prci = PLL_REFSEL(1) | PLL_BYPASS(1); in soc_early_init_hook()
36 /* refr = 8 MHz. */ in soc_early_init_hook()
[all …]
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu700/ |
| D | clock.c | 13 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
20 /* HACK to get the '1 full controller clock cycle'. */ in wait_controller_cycle()
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
31 * Note: Valid PLL VCO range is 2400MHz to 4800MHz
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
38 PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */ in soc_early_init_hook()
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in soc_early_init_hook()
40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/ |
| D | soc.c | 20 /* Move M4 core to specific RDC domain 1 */ in SOC_RdcInit()
27 * The M4 core is running at domain 1, enable clock gate for in SOC_RdcInit()
28 * Iomux to run at domain 1. in SOC_RdcInit()
39 * The M4 core is running at domain 1, enable the PLL clock sources in SOC_RdcInit()
40 * to domain 1. in SOC_RdcInit()
42 /* Enable SysPLL1 to Domain 1 */ in SOC_RdcInit()
44 /* Enable SysPLL2 to Domain 1 */ in SOC_RdcInit()
46 /* Enable SysPLL3 to Domain 1 */ in SOC_RdcInit()
48 /* Enable AudioPLL1 to Domain 1 */ in SOC_RdcInit()
50 /* Enable AudioPLL2 to Domain 1 */ in SOC_RdcInit()
[all …]
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcm-pcc.yaml | 14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
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| D | st,stm32u5-msi-clock.yaml | 22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
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| D | nuvoton,npcx-pcc.yaml | 14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
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| D | st,stm32g0-hsi-clock.yaml | 6 On STM32G0, HSI is a 16MHz fixed clock.
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
17 - 32 ==> HSISYS = 0.5MHz
18 - 64 ==> HSISYS = 0.25MHZ
19 - 128 ==> HSISYS = 0.125MHz
[all …]
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| D | st,stm32c0-hsi-clock.yaml | 6 On STM32C0, HSI is a 48MHz fixed clock.
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
[all …]
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| D | st,stm32-msi-clock.yaml | 19 - 1 # range 1 around 200 kHz
22 - 4 # range 4 around 1M Hz
23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
|
| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 20 /* Move M7 core to specific RDC domain 1 */ in SOC_RdcInit()
32 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in SOC_RdcInit()
33 * in domain 1 in the CCM. In this way, to ensure the clock of the peripherals used by M in SOC_RdcInit()
46 /* Enable the CCGR gate for SysPLL1 in Domain 1 */ in SOC_RdcInit()
48 /* Enable the CCGR gate for SysPLL2 in Domain 1 */ in SOC_RdcInit()
50 /* Enable the CCGR gate for SysPLL3 in Domain 1 */ in SOC_RdcInit()
53 /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ in SOC_RdcInit()
64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
[all …]
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| /Zephyr-latest/dts/arm/nuvoton/npcm/ |
| D | npcm4.dtsi | 17 reg-io-width = <1>;
27 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
29 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
30 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
31 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
32 ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
33 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
34 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
|
| /Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/ |
| D | soc.c | 20 /* Move M4 core to specific RDC domain 1 */ in SOC_RdcInit()
27 * The M4 core is running at domain 1, enable clock gate for in SOC_RdcInit()
28 * Iomux to run at domain 1. in SOC_RdcInit()
37 * The M4 core is running at domain 1, enable the PLL clock sources in SOC_RdcInit()
38 * to domain 1. in SOC_RdcInit()
56 CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); in SOC_ClockInit()
57 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
65 CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U); in SOC_ClockInit()
71 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
73 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/ |
| D | cy8ckit_062s2_ai.dts | 57 clock-div = <1>;
61 /* CM4 core clock = 100MHz
62 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
65 clock-div = <1>;
68 /* CM0+ core clock = 50MHz
69 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
75 /* PERI core clock = 100MHz
76 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
79 clock-div = <1>;
|
| /Zephyr-latest/boards/infineon/cy8cproto_063_ble/ |
| D | cy8cproto_063_ble.dts | 99 clock-div = <1>;
103 /* CM4 core clock = 100MHz
104 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
107 clock-div = <1>;
110 /* CM0+ core clock = 50MHz
111 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
117 /* PERI core clock = 100MHz
118 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
121 clock-div = <1>;
|
| /Zephyr-latest/drivers/modem/ |
| D | Kconfig.hl7800 | 79 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
|
| /Zephyr-latest/dts/bindings/cpu/ |
| D | espressif,xtensa-lx6.yaml | 16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
17 - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz
24 - 1
|
| D | espressif,xtensa-lx7.yaml | 16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
17 - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)
24 - 1
|
| D | espressif,riscv.yaml | 16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
17 - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz.
23 - 1
29 description: Value of the external XTAL connected to ESP32. This is typically 40 MHz.
|
| /Zephyr-latest/include/zephyr/dt-bindings/ethernet/ |
| D | xlnx_gem.h | 28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
38 #define XLNX_GEM_LINK_SPEED_10MBIT 1
44 #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_64BIT 1
[all …]
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | soc.c | 23 COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
38 #define LCO_Power_CTRL BIT(1)
39 /* LC Oscillator Control Register 1 */
40 #define LDO_Power_CTRL BIT(1)
45 #define AUTO_CAL_ENABLE BIT(1)
55 pllfreq = MHZ(8); in chip_get_pll_freq()
57 case 1: in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
[all …]
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| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | cpuclk.c | 13 * * power-on default is 26Mhz, confirmed with a hacked SOF that
15 * * The original driver has a 13Mhz mode too, but it doesn't work (it
16 * hits all the same code and data paths as 26MHz and acts as a
35 #define MTK_PLL_CON4_ISO_EN BIT(1)
61 #define MTK_CK_CG_SW 1
63 const struct { uint16_t mhz; bool pll; uint32_t pll_con2; } freqs[] = { member
73 * an OS timer driver yet. Use the 13 MHz timer hardware directly.
91 delay_us(1); in set_pll_power()
93 delay_us(1); in set_pll_power()
98 delay_us(1); in set_pll_power()
[all …]
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu500/ |
| D | clock.c | 12 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
18 * Switch the clock source to 1GHz PLL from 33.333MHz oscillator on the HiFive
25 PLL_R(0) | /* input divider: Fin / (0 + 1) = 33.33MHz */ in soc_early_init_hook()
26 PLL_F(59) | /* VCO: 2 x (59 + 1) = 120 = 3999.6MHz */ in soc_early_init_hook()
27 PLL_Q(2) | /* output divider: VCO / 2^2 = 999.9MHz */ in soc_early_init_hook()
31 while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0) { in soc_early_init_hook()
|
| /Zephyr-latest/dts/bindings/sensor/ |
| D | ti,fdc2x1x.yaml | 46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
58 The sensor performs conversion on Channel 0 to 1 by default after
63 1 = Ch0, Ch1, Ch2 (FDC2114, FDC2214 only)
67 - 1
81 1 = Perform continuous conversions on Channel 1
86 - 1
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
[all …]
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| /Zephyr-latest/boards/infineon/cy8cproto_062_4343w/ |
| D | cy8cproto_062_4343w.dts | 64 murata-1dx {
106 clock-div = <1>;
110 /* CM4 core clock = 100MHz
111 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
114 clock-div = <1>;
117 /* CM0+ core clock = 50MHz
118 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
124 /* PERI core clock = 100MHz
125 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
128 clock-div = <1>;
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | pll_hse_550.overlay | 14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
21 div-p = <1>;
31 d1cpre = <1>;
32 hpre = <2>; /* HCLK: 275 MHz */
33 d1ppre = <2>; /* APB1: 137.5 MHz */
34 d2ppre1 = <2>; /* APB2: 137.5 MHz */
35 d2ppre2 = <2>; /* APB3: 137.5 MHz */
36 d3ppre = <2>; /* APB4: 137.5 MHz */
|
