20 	/* Move M4 core to specific RDC domain 1 */  in SOC_RdcInit()
27 	 * The M4 core is running at domain 1, enable clock gate for  in SOC_RdcInit()
28 	 * Iomux to run at domain 1.  in SOC_RdcInit()
37 	 * The M4 core is running at domain 1, enable the PLL clock sources  in SOC_RdcInit()
38 	 * to domain 1.  in SOC_RdcInit()
56 	CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);  in SOC_ClockInit()
57 	/* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */  in SOC_ClockInit()
65 	CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 1U);  in SOC_ClockInit()
71 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
73 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
74 	CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);  in SOC_ClockInit()
77 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
79 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
80 	CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);  in SOC_ClockInit()
83 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
85 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
86 	CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);  in SOC_ClockInit()
89 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
91 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
92 	CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);  in SOC_ClockInit()