20 	/* Move M4 core to specific RDC domain 1 */  in SOC_RdcInit()
27 	 * The M4 core is running at domain 1, enable clock gate for  in SOC_RdcInit()
28 	 * Iomux to run at domain 1.  in SOC_RdcInit()
39 	 * The M4 core is running at domain 1, enable the PLL clock sources  in SOC_RdcInit()
40 	 * to domain 1.  in SOC_RdcInit()
42 	/* Enable SysPLL1 to Domain 1 */  in SOC_RdcInit()
44 	/* Enable SysPLL2 to Domain 1 */  in SOC_RdcInit()
46 	/* Enable SysPLL3 to Domain 1 */  in SOC_RdcInit()
48 	/* Enable AudioPLL1 to Domain 1 */  in SOC_RdcInit()
50 	/* Enable AudioPLL2 to Domain 1 */  in SOC_RdcInit()
52 	/* Enable VideoPLL1 to Domain 1 */  in SOC_RdcInit()
71 	.postDiv = 1U, /* AUDIO PLL2 frequency  = 722534399HZ */
93 	CLOCK_SetRootDivider(kCLOCK_RootM4, 1U, 2U);  in SOC_ClockInit()
97 	CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);  in SOC_ClockInit()
98 	/* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */  in SOC_ClockInit()
101 	/* Set root clock to 800MHZ/ 2= 400MHZ */  in SOC_ClockInit()
102 	CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U);  in SOC_ClockInit()
108 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
110 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
111 	CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);  in SOC_ClockInit()
114 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
116 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
117 	CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);  in SOC_ClockInit()
120 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
122 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
123 	CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);  in SOC_ClockInit()
126 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
128 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
129 	CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);  in SOC_ClockInit()
135 	/* Set ECSPI1 source to SYSTEM PLL1 800MHZ */  in SOC_ClockInit()
137 	/* Set root clock to 800MHZ / 10 = 80MHZ */  in SOC_ClockInit()
142 	/* Set ECSPI2 source to SYSTEM PLL1 800MHZ */  in SOC_ClockInit()
144 	/* Set root clock to 800MHZ / 10 = 80MHZ */  in SOC_ClockInit()
149 	/* Set ECSPI3 source to SYSTEM PLL1 800MHZ */  in SOC_ClockInit()
151 	/* Set root clock to 800MHZ / 10 = 80MHZ */  in SOC_ClockInit()