Lines Matching +full:1 +full:mhz
23 COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
38 #define LCO_Power_CTRL BIT(1)
39 /* LC Oscillator Control Register 1 */
40 #define LDO_Power_CTRL BIT(1)
45 #define AUTO_CAL_ENABLE BIT(1)
55 pllfreq = MHZ(8); in chip_get_pll_freq()
57 case 1: in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
67 pllfreq = MHZ(48); in chip_get_pll_freq()
70 pllfreq = MHZ(64); in chip_get_pll_freq()
73 pllfreq = MHZ(72); in chip_get_pll_freq()
76 pllfreq = MHZ(96); in chip_get_pll_freq()
121 * PLL frequency setting = 4 (48MHz)
122 * MCU div = 0 (PLL / 1 = 48 mhz)
123 * FND div = 0 (PLL / 1 = 48 mhz)
124 * USB div = 0 (PLL / 1 = 48 mhz)
125 * UART div = 1 (PLL / 2 = 24 mhz)
126 * SMB div = 1 (PLL / 2 = 24 mhz)
127 * SSPI div = 1 (PLL / 2 = 24 mhz)
128 * EC div = 6 (FND / 6 = 8 mhz)
129 * JTAG div = 1 (PLL / 2 = 24 mhz)
130 * PWM div = 0 (PLL / 1 = 48 mhz)
131 * USBPD div = 5 (PLL / 6 = 8 mhz)
137 .div_uart = 1,
138 .div_smb = 1,
139 .div_sspi = 1,
141 .div_ec = 1,
145 .div_jtag = 1,
149 * PLL frequency setting = 7 (96MHz)
150 * MCU div = 1 (PLL / 2 = 48 mhz)
151 * FND div = 1 (PLL / 2 = 48 mhz)
152 * USB div = 1 (PLL / 2 = 48 mhz)
153 * UART div = 3 (PLL / 4 = 24 mhz)
154 * SMB div = 3 (PLL / 4 = 24 mhz)
155 * SSPI div = 3 (PLL / 4 = 24 mhz)
156 * EC div = 6 (FND / 6 = 8 mhz)
157 * JTAG div = 3 (PLL / 4 = 24 mhz)
158 * PWM div = 1 (PLL / 2 = 48 mhz)
159 * USBPD div = 11 (PLL / 12 = 8 mhz)
162 .div_mcu = 1,
163 .div_fnd = 1,
164 .div_usb = 1,
169 .div_ec = 1,
174 .div_pwm = 1,
459 } else if (port == 1) { in ite_it8xxx2_init()