13 BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 1,
20 	 * HFXOSC (16 MHz) is used to produce coreclk (and therefore tlclk /  in soc_early_init_hook()
22 	 * - 16 MHz (bypass HFPLL).  in soc_early_init_hook()
23 	 * - 48 MHz - 320 MHz, in 8 MHz steps (use HFPLL).  in soc_early_init_hook()
25 	BUILD_ASSERT(MHZ(16) == CORECLK_HZ ||  in soc_early_init_hook()
26 		(MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ &&  in soc_early_init_hook()
27 		(CORECLK_HZ % MHZ(8)) == 0),  in soc_early_init_hook()
32 	if (MHZ(16) == CORECLK_HZ) {  in soc_early_init_hook()
34 		prci = PLL_REFSEL(1) | PLL_BYPASS(1);  in soc_early_init_hook()
36 		/* refr = 8 MHz. */  in soc_early_init_hook()
40 		/* Select Q divisor to produce vco on [384 MHz, 768 MHz]. */  in soc_early_init_hook()
41 		if (MHZ(768) / 8 >= CORECLK_HZ) {  in soc_early_init_hook()
43 		} else if (MHZ(768) / 4 >= CORECLK_HZ) {  in soc_early_init_hook()
49 		const int pll_f = ((CORECLK_HZ / MHZ(1)) >> (4 - pll_q)) - 1;  in soc_early_init_hook()
51 		prci = PLL_REFSEL(1) | PLL_R(pll_r) | PLL_F(pll_f) | PLL_Q(pll_q);  in soc_early_init_hook()
55 	PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));  in soc_early_init_hook()
56 	PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);  in soc_early_init_hook()
57 	PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);  in soc_early_init_hook()