20 	/* Move M7 core to specific RDC domain 1 */  in SOC_RdcInit()
32 	 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL  in SOC_RdcInit()
33 	 * in domain 1 in the CCM. In this way, to ensure the clock of the peripherals used by M  in SOC_RdcInit()
46 	/* Enable the CCGR gate for SysPLL1 in Domain 1 */  in SOC_RdcInit()
48 	/* Enable the CCGR gate for SysPLL2 in Domain 1 */  in SOC_RdcInit()
50 	/* Enable the CCGR gate for SysPLL3 in Domain 1 */  in SOC_RdcInit()
53 	/* Enable the CCGR gate for VideoPLL1 in Domain 1 */  in SOC_RdcInit()
64 	.postDiv = 2U, /*!< SYSTEM PLL1 frequency  = 800MHZ */
72 	.postDiv = 1U, /*!< SYSTEM PLL2 frequency  = 1000MHZ */
80 	.postDiv = 2U, /*!< SYSTEM PLL3 frequency  = 600MHZ */
88 	 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2  in SOC_ClockInit()
100 	CLOCK_SetRootDivider(kCLOCK_RootM7, 1U, 1U);  in SOC_ClockInit()
104 	/* Set root clock freq to 133M / 1= 133MHZ */  in SOC_ClockInit()
105 	CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U);  in SOC_ClockInit()
111 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
113 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
114 	CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);  in SOC_ClockInit()
117 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
119 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
120 	CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);  in SOC_ClockInit()
123 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
125 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
126 	CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);  in SOC_ClockInit()
129 	/* Set UART source to SysPLL1 Div10 80MHZ */  in SOC_ClockInit()
131 	/* Set root clock to 80MHZ/ 1= 80MHZ */  in SOC_ClockInit()
132 	CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);  in SOC_ClockInit()
138 	/* Set ECSPI1 source to SYSTEM PLL1 800MHZ */  in SOC_ClockInit()
140 	/* Set root clock to 800MHZ / 10 = 80MHZ */  in SOC_ClockInit()
145 	/* Set ECSPI2 source to SYSTEM PLL1 800MHZ */  in SOC_ClockInit()
147 	/* Set root clock to 800MHZ / 10 = 80MHZ */  in SOC_ClockInit()
152 	/* Set ECSPI3 source to SYSTEM PLL1 800MHZ */  in SOC_ClockInit()
154 	/* Set root clock to 800MHZ / 10 = 80MHZ */  in SOC_ClockInit()