1# Copyright (c) 2022 STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 HSI Clock node description for STM32G0 devices
6  On STM32G0, HSI is a 16MHz fixed clock.
7
8  It also produces a HSISYS secondary clk which can be used as system clock
9  source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
10  SYSCLK = HSI16 / HSI DIV
11        enum:
12        - 1 ==> HSISYS = 16MHZ
13        - 2 ==> HSISYS = 8MHZ
14        - 4 ==> HSISYS = 4MHZ
15        - 8 ==> HSISYS = 2MHZ
16        - 16 ==> HSISYS = 1MHZ
17        - 32 ==> HSISYS = 0.5MHz
18        - 64 ==> HSISYS = 0.25MHZ
19        - 128 ==> HSISYS = 0.125MHz
20
21compatible: "st,stm32g0-hsi-clock"
22
23include: [fixed-clock.yaml]
24
25properties:
26  hsi-div:
27    type: int
28    required: true
29    description: |
30      HSI clock divider. Configures the output HSI clock frequency (HSISYS),
31      It does not apply to HSI clk selected as peripheral source clock
32      (eg: RNG clk driven by HSI)
33    enum:
34      - 1
35      - 2
36      - 4
37      - 8
38      - 16
39      - 32
40      - 64
41      - 128
42