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Searched refs:CFG1 (Results 1 – 25 of 139) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_spi.h1108 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); in LL_SPI_SetUDRConfiguration()
1121 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1261 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); in LL_SPI_SetBaudRatePrescaler()
1282 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); in LL_SPI_GetBaudRatePrescaler()
1422 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1462 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1491 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1518 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
1530 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_EnableCRC()
1541 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_DisableCRC()
[all …]
Dstm32u5xx_ll_ucpd.h348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable()
360 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Disable()
371 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); in LL_UCPD_IsEnabled()
392 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); in LL_UCPD_SetRxOrderSet()
409 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); in LL_UCPD_SetPSCClk()
421 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); in LL_UCPD_SetTransWin()
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
445 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); in LL_UCPD_SetHbitClockDiv()
1685 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMAEnable()
1696 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMADisable()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_spi.h1103 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); in LL_SPI_SetUDRConfiguration()
1116 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1256 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); in LL_SPI_SetBaudRatePrescaler()
1277 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); in LL_SPI_GetBaudRatePrescaler()
1417 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1457 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1486 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1513 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
1525 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_EnableCRC()
1536 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_DisableCRC()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_ucpd.h346 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable()
358 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Disable()
369 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); in LL_UCPD_IsEnabled()
390 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); in LL_UCPD_SetRxOrderSet()
407 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); in LL_UCPD_SetPSCClk()
419 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); in LL_UCPD_SetTransWin()
431 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
443 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); in LL_UCPD_SetHbitClockDiv()
1606 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMAEnable()
1617 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMADisable()
[all …]
Dstm32n6xx_ll_spi.h1021 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); in LL_SPI_SetUDRConfiguration()
1034 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1174 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); in LL_SPI_SetBaudRatePrescaler()
1195 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); in LL_SPI_GetBaudRatePrescaler()
1335 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1375 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1404 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1431 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
1443 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_EnableCRC()
1454 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_DisableCRC()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_ucpd.h348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable()
360 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Disable()
371 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); in LL_UCPD_IsEnabled()
392 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); in LL_UCPD_SetRxOrderSet()
409 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); in LL_UCPD_SetPSCClk()
421 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); in LL_UCPD_SetTransWin()
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
445 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); in LL_UCPD_SetHbitClockDiv()
1674 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMAEnable()
1685 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMADisable()
[all …]
Dstm32h7rsxx_ll_spi.h1021 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); in LL_SPI_SetUDRConfiguration()
1034 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1174 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); in LL_SPI_SetBaudRatePrescaler()
1195 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); in LL_SPI_GetBaudRatePrescaler()
1335 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1375 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1404 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1431 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
1443 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_EnableCRC()
1454 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_DisableCRC()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_ucpd.h348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable()
360 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Disable()
371 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); in LL_UCPD_IsEnabled()
392 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); in LL_UCPD_SetRxOrderSet()
409 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); in LL_UCPD_SetPSCClk()
421 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); in LL_UCPD_SetTransWin()
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
445 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); in LL_UCPD_SetHbitClockDiv()
1685 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMAEnable()
1696 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMADisable()
[all …]
Dstm32h5xx_ll_spi.h1021 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); in LL_SPI_SetUDRConfiguration()
1034 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1174 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); in LL_SPI_SetBaudRatePrescaler()
1195 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); in LL_SPI_GetBaudRatePrescaler()
1335 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1375 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1404 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1431 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
1443 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_EnableCRC()
1454 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_DisableCRC()
[all …]
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_ucpd.h348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable()
360 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Disable()
371 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); in LL_UCPD_IsEnabled()
392 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); in LL_UCPD_SetRxOrderSet()
409 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); in LL_UCPD_SetPSCClk()
421 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); in LL_UCPD_SetTransWin()
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
445 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); in LL_UCPD_SetHbitClockDiv()
1652 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMAEnable()
1663 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMADisable()
[all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_ucpd.h348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable()
360 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Disable()
371 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); in LL_UCPD_IsEnabled()
392 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); in LL_UCPD_SetRxOrderSet()
409 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); in LL_UCPD_SetPSCClk()
421 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); in LL_UCPD_SetTransWin()
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
445 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); in LL_UCPD_SetHbitClockDiv()
1652 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMAEnable()
1663 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMADisable()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_ucpd.h348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable()
360 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Disable()
371 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); in LL_UCPD_IsEnabled()
392 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); in LL_UCPD_SetRxOrderSet()
409 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); in LL_UCPD_SetPSCClk()
421 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); in LL_UCPD_SetTransWin()
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); in LL_UCPD_SetIfrGap()
445 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); in LL_UCPD_SetHbitClockDiv()
1663 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMAEnable()
1674 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); in LL_UCPD_RxDMADisable()
[all …]
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_spi.h1059 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); in LL_SPI_SetUDRConfiguration()
1073 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1089 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection); in LL_SPI_SetUDRDetection()
1103 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET)); in LL_SPI_GetUDRDetection()
1240 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate); in LL_SPI_SetBaudRatePrescaler()
1259 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR)); in LL_SPI_GetBaudRatePrescaler()
1399 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1439 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1468 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1495 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_spi.h1059 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); in LL_SPI_SetUDRConfiguration()
1073 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1089 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection); in LL_SPI_SetUDRDetection()
1103 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET)); in LL_SPI_GetUDRDetection()
1240 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate); in LL_SPI_SetBaudRatePrescaler()
1259 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR)); in LL_SPI_GetBaudRatePrescaler()
1399 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1439 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1468 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1495 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_spi_ex.c190 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); in HAL_SPIEx_ConfigureUnderrun()
198 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); in HAL_SPIEx_ConfigureUnderrun()
239 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); in HAL_SPIEx_EnableDelayReadDataSampling()
246 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); in HAL_SPIEx_EnableDelayReadDataSampling()
285 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); in HAL_SPIEx_DisableDelayReadDataSampling()
292 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); in HAL_SPIEx_DisableDelayReadDataSampling()
Dstm32h5xx_hal_i2s.c1507 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2S_Transmit_DMA()
1510 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_Transmit_DMA()
1636 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2S_Receive_DMA()
1639 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2S_Receive_DMA()
1702 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1769 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1772 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1831 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1834 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1974 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_DMAStop()
[all …]
Dstm32h5xx_hal_spi.c387 crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; in HAL_SPI_Init()
414 …WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_le… in HAL_SPI_Init()
477 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); in HAL_SPI_Init()
2116 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2182 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2277 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2379 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2458 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2574 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2651 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_TransmitReceive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_i2s.c1467 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2S_Transmit_DMA()
1470 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_Transmit_DMA()
1553 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2S_Receive_DMA()
1556 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2S_Receive_DMA()
1619 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1643 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1646 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1662 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1665 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1805 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_DMAStop()
[all …]
Dstm32h7xx_hal_spi.c367 crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; in HAL_SPI_Init()
394 …WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_le… in HAL_SPI_Init()
460 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0); in HAL_SPI_Init()
462 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1); in HAL_SPI_Init()
2176 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2203 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2287 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2350 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2417 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2496 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_i2s.c1491 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2S_Transmit_DMA()
1494 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_Transmit_DMA()
1625 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2S_Receive_DMA()
1628 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2S_Receive_DMA()
1691 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1758 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1761 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1825 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1828 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1968 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_DMAStop()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_i2s.c1512 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2S_Transmit_DMA()
1515 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_Transmit_DMA()
1641 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2S_Receive_DMA()
1644 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2S_Receive_DMA()
1707 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1774 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1777 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1836 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN)) in HAL_I2SEx_TransmitReceive_DMA()
1839 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_I2SEx_TransmitReceive_DMA()
1979 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_I2S_DMAStop()
[all …]
Dstm32h7rsxx_hal_spi.c381 crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; in HAL_SPI_Init()
408 …WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_le… in HAL_SPI_Init()
465 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); in HAL_SPI_Init()
1879 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
1954 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2041 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2152 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2224 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2346 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2429 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_TransmitReceive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_spi.c363 crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; in HAL_SPI_Init()
390 …WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_le… in HAL_SPI_Init()
450 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0); in HAL_SPI_Init()
452 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1); in HAL_SPI_Init()
2065 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2093 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2180 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2244 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2316 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2402 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_spi.c379 crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; in HAL_SPI_Init()
406 …WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_le… in HAL_SPI_Init()
463 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); in HAL_SPI_Init()
1877 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
1943 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2029 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2131 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2200 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2312 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2389 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_TransmitReceive_DMA()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_spi.c385 crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; in HAL_SPI_Init()
412 …WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_le… in HAL_SPI_Init()
475 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); in HAL_SPI_Init()
2140 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2206 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_Transmit_DMA()
2301 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2403 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_Receive_DMA()
2482 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2598 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); in HAL_SPI_TransmitReceive_DMA()
2675 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); in HAL_SPI_TransmitReceive_DMA()
[all …]

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