1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_SPI_H
21 #define STM32H5xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private variables ---------------------------------------------------------*/
41
42 /* Private constants ---------------------------------------------------------*/
43
44 /* Private macros ------------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
46 * @{
47 */
48 /**
49 * @}
50 */
51
52 /* Exported types ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup SPI_LL_Exported_Types SPI Exported Types
55 * @{
56 */
57
58 /**
59 * @brief SPI Init structures definition
60 */
61 typedef struct
62 {
63 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
64 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
65
66 This feature can be modified afterwards using unitary function
67 @ref LL_SPI_SetTransferDirection().*/
68
69 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
70 This parameter can be a value of @ref SPI_LL_EC_MODE.
71
72 This feature can be modified afterwards using unitary function
73 @ref LL_SPI_SetMode().*/
74
75 uint32_t DataWidth; /*!< Specifies the SPI data width.
76 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_SPI_SetDataWidth().*/
80
81 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
82 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
83
84 This feature can be modified afterwards using unitary function
85 @ref LL_SPI_SetClockPolarity().*/
86
87 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
88 This parameter can be a value of @ref SPI_LL_EC_PHASE.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_SPI_SetClockPhase().*/
92
93 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
94 or by software using the SSI bit.
95
96 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
97
98 This feature can be modified afterwards using unitary function
99 @ref LL_SPI_SetNSSMode().*/
100
101 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
102 the transmit and receive SCK clock.
103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
104 @note The communication clock is derived from the master clock.
105 The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_SPI_SetTransferBitOrder().*/
115
116 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
117 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
118
119 This feature can be modified afterwards using unitary functions
120 @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
121
122 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
123 This parameter must be a number between Min_Data = 0x00
124 and Max_Data = 0xFFFFFFFF.
125
126 This feature can be modified afterwards using unitary function
127 @ref LL_SPI_SetCRCPolynomial().*/
128
129 } LL_SPI_InitTypeDef;
130
131 /**
132 * @}
133 */
134 #endif /*USE_FULL_LL_DRIVER*/
135
136 /* Exported types ------------------------------------------------------------*/
137
138 /* Exported constants --------------------------------------------------------*/
139 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
140 * @{
141 */
142
143 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
144 * @brief Flags defines which can be used with LL_SPI_ReadReg function
145 * @{
146 */
147 #define LL_SPI_SR_RXP (SPI_SR_RXP)
148 #define LL_SPI_SR_TXP (SPI_SR_TXP)
149 #define LL_SPI_SR_DXP (SPI_SR_DXP)
150 #define LL_SPI_SR_EOT (SPI_SR_EOT)
151 #define LL_SPI_SR_TXTF (SPI_SR_TXTF)
152 #define LL_SPI_SR_UDR (SPI_SR_UDR)
153 #define LL_SPI_SR_CRCE (SPI_SR_CRCE)
154 #define LL_SPI_SR_MODF (SPI_SR_MODF)
155 #define LL_SPI_SR_OVR (SPI_SR_OVR)
156 #define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
157 #define LL_SPI_SR_SUSP (SPI_SR_SUSP)
158 #define LL_SPI_SR_TXC (SPI_SR_TXC)
159 #define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
160 /**
161 * @}
162 */
163
164 /** @defgroup SPI_LL_EC_IT IT Defines
165 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
166 * @{
167 */
168 #define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
169 #define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
170 #define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
171 #define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
172 #define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
173 #define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
174 #define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
175 #define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
176 #define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
177 #define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
178 /**
179 * @}
180 */
181
182 /** @defgroup SPI_LL_EC_MODE Mode
183 * @{
184 */
185 #define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
186 #define LL_SPI_MODE_SLAVE (0x00000000UL)
187 /**
188 * @}
189 */
190
191 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
192 * @{
193 */
194 #define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
195 #define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
196 /**
197 * @}
198 */
199
200 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
201 * @{
202 */
203 #define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
204 #define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
205 #define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
206 #define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
207 #define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
208 #define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
209 #define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
210 #define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
211 #define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
212 #define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
213 #define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
214 #define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
215 #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
216 #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
217 #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
218 #define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
219 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
220 /**
221 * @}
222 */
223
224 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
225 * @{
226 */
227 #define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
228 #define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
229 #define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
230 #define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
231 #define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
232 #define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
233 #define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
234 #define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
235 #define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
236 #define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
237 #define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
238 #define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
239 #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
240 #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
241 #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
242 #define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
243 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
244 /**
245 * @}
246 */
247
248 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
249 * @{
250 */
251 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
252 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
253 /**
254 * @}
255 */
256
257 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
258 * @{
259 */
260 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
261 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
262 /**
263 * @}
264 */
265
266 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
267 * @{
268 */
269 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
270 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG)
271 /**
272 * @}
273 */
274
275 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
276 * @{
277 */
278 #define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
279 #define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
280 /**
281 * @}
282 */
283
284 /** @defgroup SPI_LL_EC_PHASE Phase
285 * @{
286 */
287 #define LL_SPI_PHASE_1EDGE (0x00000000UL)
288 #define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
289 /**
290 * @}
291 */
292
293 /** @defgroup SPI_LL_EC_POLARITY Polarity
294 * @{
295 */
296 #define LL_SPI_POLARITY_LOW (0x00000000UL)
297 #define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
298 /**
299 * @}
300 */
301
302 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
303 * @{
304 */
305 #define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
306 #define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
307 /**
308 * @}
309 */
310
311 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
312 * @{
313 */
314 #define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS)
315 #define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
316 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
317 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
318 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
319 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
320 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
321 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
322 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
323 /**
324 * @}
325 */
326
327 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
328 * @{
329 */
330 #define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
331 #define LL_SPI_MSB_FIRST (0x00000000UL)
332 /**
333 * @}
334 */
335
336 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
337 * @{
338 */
339 #define LL_SPI_FULL_DUPLEX (0x00000000UL)
340 #define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
341 #define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
342 #define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
343 #define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
344 /**
345 * @}
346 */
347
348 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
349 * @{
350 */
351 #define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
352 #define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
353 #define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
354 #define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
355 #define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
356 #define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
357 #define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
358 #define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
359 #define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
360 #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
361 #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
362 #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
363 #define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
364 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
365 #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
366 #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
367 #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
368 #define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
369 #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
370 #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
371 #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
372 #define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
373 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
374 #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
375 #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
376 #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
377 #define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
378 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
379 #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
380 #define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
381 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
382 #define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
383 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
384 #define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
385 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
386 /**
387 * @}
388 */
389
390 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
391 * @{
392 */
393 #define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
394 #define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
395 #define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
396 #define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
397 #define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
398 #define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
399 #define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
400 #define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
401 #define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
402 #define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
403 #define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
404 #define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
405 #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
406 #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
407 #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
408 #define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
409 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
410 /**
411 * @}
412 */
413
414 #if defined(USE_FULL_LL_DRIVER)
415
416 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
417 * @{
418 */
419 #define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
420 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
421 /**
422 * @}
423 */
424 #endif /* USE_FULL_LL_DRIVER */
425
426 /** @defgroup SPI_LL_EC_CRC CRC
427 * @{
428 */
429 #define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
430 #define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
431 #define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
432 #define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
433 #define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
434 #define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
435 #define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
436 #define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
437 #define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
438 #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
439 #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
440 #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
441 #define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
442 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
443 #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
444 #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
445 #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
446 #define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
447 #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
448 #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
449 #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
450 #define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
451 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
452 #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
453 #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
454 #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
455 #define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
456 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
457 #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
458 #define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
459 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
460 #define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
461 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
462 #define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
463 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
464 /**
465 * @}
466 */
467
468 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
469 * @{
470 */
471 #define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
472 #define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
473 #define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
474 /**
475 * @}
476 */
477
478 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
479 * @{
480 */
481 #define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
482 #define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
483 #define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
484 #define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
485 /**
486 * @}
487 */
488
489 /**
490 * @}
491 */
492
493 /* Exported macro ------------------------------------------------------------*/
494 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
495 * @{
496 */
497
498 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
499 * @{
500 */
501
502 /**
503 * @brief Write a value in SPI register
504 * @param __INSTANCE__ SPI Instance
505 * @param __REG__ Register to be written
506 * @param __VALUE__ Value to be written in the register
507 * @retval None
508 */
509 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
510
511 /**
512 * @brief Read a value in SPI register
513 * @param __INSTANCE__ SPI Instance
514 * @param __REG__ Register to be read
515 * @retval Register value
516 */
517 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
518 /**
519 * @}
520 */
521
522 /**
523 * @}
524 */
525
526
527 /* Exported functions --------------------------------------------------------*/
528
529 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
530 * @{
531 */
532
533 /** @defgroup SPI_LL_EF_Configuration Configuration
534 * @{
535 */
536
537 /**
538 * @brief Enable SPI peripheral
539 * @rmtoll CR1 SPE LL_SPI_Enable
540 * @param SPIx SPI Instance
541 * @retval None
542 */
LL_SPI_Enable(SPI_TypeDef * SPIx)543 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
544 {
545 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
546 }
547
548 /**
549 * @brief Disable SPI peripheral
550 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
551 * @rmtoll CR1 SPE LL_SPI_Disable
552 * @param SPIx SPI Instance
553 * @retval None
554 */
LL_SPI_Disable(SPI_TypeDef * SPIx)555 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
556 {
557 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
558 }
559
560 /**
561 * @brief Check if SPI peripheral is enabled
562 * @rmtoll CR1 SPE LL_SPI_IsEnabled
563 * @param SPIx SPI Instance
564 * @retval State of bit (1 or 0)
565 */
LL_SPI_IsEnabled(const SPI_TypeDef * SPIx)566 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
567 {
568 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
569 }
570
571 /**
572 * @brief Swap the MOSI and MISO pin
573 * @note This configuration can not be changed when SPI is enabled.
574 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
575 * @param SPIx SPI Instance
576 * @retval None
577 */
LL_SPI_EnableIOSwap(SPI_TypeDef * SPIx)578 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
579 {
580 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
581 }
582
583 /**
584 * @brief Restore default function for MOSI and MISO pin
585 * @note This configuration can not be changed when SPI is enabled.
586 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
587 * @param SPIx SPI Instance
588 * @retval None
589 */
LL_SPI_DisableIOSwap(SPI_TypeDef * SPIx)590 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
591 {
592 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
593 }
594
595 /**
596 * @brief Check if MOSI and MISO pin are swapped
597 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
598 * @param SPIx SPI Instance
599 * @retval State of bit (1 or 0)
600 */
LL_SPI_IsEnabledIOSwap(const SPI_TypeDef * SPIx)601 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
602 {
603 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
604 }
605
606 /**
607 * @brief Enable GPIO control
608 * @note This configuration can not be changed when SPI is enabled.
609 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
610 * @param SPIx SPI Instance
611 * @retval None
612 */
LL_SPI_EnableGPIOControl(SPI_TypeDef * SPIx)613 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
614 {
615 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
616 }
617
618 /**
619 * @brief Disable GPIO control
620 * @note This configuration can not be changed when SPI is enabled.
621 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
622 * @param SPIx SPI Instance
623 * @retval None
624 */
LL_SPI_DisableGPIOControl(SPI_TypeDef * SPIx)625 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
626 {
627 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
628 }
629
630 /**
631 * @brief Check if GPIO control is active
632 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
633 * @param SPIx SPI Instance
634 * @retval State of bit (1 or 0)
635 */
LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef * SPIx)636 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
637 {
638 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
639 }
640
641 /**
642 * @brief Set SPI Mode to Master or Slave
643 * @note This configuration can not be changed when SPI is enabled.
644 * @rmtoll CFG2 MASTER LL_SPI_SetMode
645 * @param SPIx SPI Instance
646 * @param Mode This parameter can be one of the following values:
647 * @arg @ref LL_SPI_MODE_MASTER
648 * @arg @ref LL_SPI_MODE_SLAVE
649 * @retval None
650 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)651 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
652 {
653 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
654 }
655
656 /**
657 * @brief Get SPI Mode (Master or Slave)
658 * @rmtoll CFG2 MASTER LL_SPI_GetMode
659 * @param SPIx SPI Instance
660 * @retval Returned value can be one of the following values:
661 * @arg @ref LL_SPI_MODE_MASTER
662 * @arg @ref LL_SPI_MODE_SLAVE
663 */
LL_SPI_GetMode(const SPI_TypeDef * SPIx)664 __STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
665 {
666 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
667 }
668
669 /**
670 * @brief Configure the Idleness applied by master between active edge of SS and first send data
671 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
672 * @param SPIx SPI Instance
673 * @param MasterSSIdleness This parameter can be one of the following values:
674 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
675 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
676 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
677 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
678 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
679 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
680 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
681 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
682 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
683 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
684 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
685 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
686 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
687 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
688 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
689 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
690 * @retval None
691 */
LL_SPI_SetMasterSSIdleness(SPI_TypeDef * SPIx,uint32_t MasterSSIdleness)692 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
693 {
694 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
695 }
696
697 /**
698 * @brief Get the configured Idleness applied by master
699 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
700 * @param SPIx SPI Instance
701 * @retval Returned value can be one of the following values:
702 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
703 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
704 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
705 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
706 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
707 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
708 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
709 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
710 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
711 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
712 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
713 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
714 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
715 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
716 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
717 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
718 */
LL_SPI_GetMasterSSIdleness(const SPI_TypeDef * SPIx)719 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
720 {
721 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
722 }
723
724 /**
725 * @brief Configure the idleness applied by master between data frame
726 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
727 * @param SPIx SPI Instance
728 * @param MasterInterDataIdleness This parameter can be one of the following values:
729 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
730 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
731 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
732 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
733 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
734 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
735 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
736 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
737 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
738 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
739 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
740 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
741 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
742 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
743 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
744 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
745 * @retval None
746 */
LL_SPI_SetInterDataIdleness(SPI_TypeDef * SPIx,uint32_t MasterInterDataIdleness)747 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
748 {
749 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
750 }
751
752 /**
753 * @brief Get the configured inter data idleness
754 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
755 * @param SPIx SPI Instance
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
758 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
759 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
760 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
761 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
762 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
763 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
764 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
765 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
766 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
767 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
768 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
769 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
770 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
771 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
772 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
773 */
LL_SPI_GetInterDataIdleness(const SPI_TypeDef * SPIx)774 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
775 {
776 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
777 }
778
779 /**
780 * @brief Set transfer size
781 * @note Count is the number of frame to be transferred
782 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
783 * @param SPIx SPI Instance
784 * @param Count 0..0xFFFF
785 * @retval None
786 */
LL_SPI_SetTransferSize(SPI_TypeDef * SPIx,uint32_t Count)787 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
788 {
789 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
790 }
791
792 /**
793 * @brief Get transfer size
794 * @note Count is the number of frame to be transferred
795 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
796 * @param SPIx SPI Instance
797 * @retval 0..0xFFFF
798 */
LL_SPI_GetTransferSize(const SPI_TypeDef * SPIx)799 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
800 {
801 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
802 }
803
804 /**
805 * @brief Lock the AF configuration of associated IOs
806 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
807 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
808 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
809 * @param SPIx SPI Instance
810 * @retval None
811 */
LL_SPI_EnableIOLock(SPI_TypeDef * SPIx)812 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
813 {
814 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
815 }
816
817 /**
818 * @brief Check if the AF configuration is locked.
819 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
820 * @param SPIx SPI Instance
821 * @retval State of bit (1 or 0)
822 */
LL_SPI_IsEnabledIOLock(const SPI_TypeDef * SPIx)823 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
824 {
825 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
826 }
827
828 /**
829 * @brief Set Tx CRC Initialization Pattern
830 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
831 * @param SPIx SPI Instance
832 * @param TXCRCInitAll This parameter can be one of the following values:
833 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
834 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
835 * @retval None
836 */
LL_SPI_SetTxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t TXCRCInitAll)837 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
838 {
839 MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll);
840 }
841
842 /**
843 * @brief Get Tx CRC Initialization Pattern
844 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
845 * @param SPIx SPI Instance
846 * @retval Returned value can be one of the following values:
847 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
848 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
849 */
LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef * SPIx)850 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
851 {
852 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
853 }
854
855 /**
856 * @brief Set Rx CRC Initialization Pattern
857 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
858 * @param SPIx SPI Instance
859 * @param RXCRCInitAll This parameter can be one of the following values:
860 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
861 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
862 * @retval None
863 */
LL_SPI_SetRxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t RXCRCInitAll)864 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
865 {
866 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
867 }
868
869 /**
870 * @brief Get Rx CRC Initialization Pattern
871 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
872 * @param SPIx SPI Instance
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
875 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
876 */
LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef * SPIx)877 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
878 {
879 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
880 }
881
882 /**
883 * @brief Set internal SS input level ignoring what comes from PIN.
884 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
885 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
886 * @param SPIx SPI Instance
887 * @param SSLevel This parameter can be one of the following values:
888 * @arg @ref LL_SPI_SS_LEVEL_HIGH
889 * @arg @ref LL_SPI_SS_LEVEL_LOW
890 * @retval None
891 */
LL_SPI_SetInternalSSLevel(SPI_TypeDef * SPIx,uint32_t SSLevel)892 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
893 {
894 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
895 }
896
897 /**
898 * @brief Get internal SS input level
899 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
900 * @param SPIx SPI Instance
901 * @retval Returned value can be one of the following values:
902 * @arg @ref LL_SPI_SS_LEVEL_HIGH
903 * @arg @ref LL_SPI_SS_LEVEL_LOW
904 */
LL_SPI_GetInternalSSLevel(const SPI_TypeDef * SPIx)905 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
906 {
907 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
908 }
909
910 /**
911 * @brief Enable CRC computation on 33/17 bits
912 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
913 * @param SPIx SPI Instance
914 * @retval None
915 */
LL_SPI_EnableFullSizeCRC(SPI_TypeDef * SPIx)916 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
917 {
918 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
919 }
920
921 /**
922 * @brief Disable CRC computation on 33/17 bits
923 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
924 * @param SPIx SPI Instance
925 * @retval None
926 */
LL_SPI_DisableFullSizeCRC(SPI_TypeDef * SPIx)927 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
928 {
929 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
930 }
931
932 /**
933 * @brief Check if Enable CRC computation on 33/17 bits is enabled
934 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
935 * @param SPIx SPI Instance
936 * @retval State of bit (1 or 0)
937 */
LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef * SPIx)938 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
939 {
940 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
941 }
942
943 /**
944 * @brief Suspend an ongoing transfer for Master configuration
945 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
946 * @param SPIx SPI Instance
947 * @retval None
948 */
LL_SPI_SuspendMasterTransfer(SPI_TypeDef * SPIx)949 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
950 {
951 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
952 }
953
954 /**
955 * @brief Start effective transfer on wire for Master configuration
956 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
957 * @param SPIx SPI Instance
958 * @retval None
959 */
LL_SPI_StartMasterTransfer(SPI_TypeDef * SPIx)960 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
961 {
962 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
963 }
964
965 /**
966 * @brief Check if there is an unfinished master transfer
967 * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
968 * @param SPIx SPI Instance
969 * @retval State of bit (1 or 0)
970 */
LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef * SPIx)971 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
972 {
973 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
974 }
975
976 /**
977 * @brief Enable Master Rx auto suspend in case of overrun
978 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
979 * @param SPIx SPI Instance
980 * @retval None
981 */
LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef * SPIx)982 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
983 {
984 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
985 }
986
987 /**
988 * @brief Disable Master Rx auto suspend in case of overrun
989 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
990 * @param SPIx SPI Instance
991 * @retval None
992 */
LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef * SPIx)993 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
994 {
995 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
996 }
997
998 /**
999 * @brief Check if Master Rx auto suspend is activated
1000 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1001 * @param SPIx SPI Instance
1002 * @retval State of bit (1 or 0)
1003 */
LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef * SPIx)1004 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
1005 {
1006 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1007 }
1008
1009 /**
1010 * @brief Set Underrun behavior
1011 * @note This configuration can not be changed when SPI is enabled.
1012 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1013 * @param SPIx SPI Instance
1014 * @param UDRConfig This parameter can be one of the following values:
1015 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1016 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1017 * @retval None
1018 */
LL_SPI_SetUDRConfiguration(SPI_TypeDef * SPIx,uint32_t UDRConfig)1019 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1020 {
1021 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1022 }
1023
1024 /**
1025 * @brief Get Underrun behavior
1026 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1027 * @param SPIx SPI Instance
1028 * @retval Returned value can be one of the following values:
1029 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1030 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1031 */
LL_SPI_GetUDRConfiguration(const SPI_TypeDef * SPIx)1032 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
1033 {
1034 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1035 }
1036
1037
1038 /**
1039 * @brief Set Serial protocol used
1040 * @note This configuration can not be changed when SPI is enabled.
1041 * @rmtoll CFG2 SP LL_SPI_SetStandard
1042 * @param SPIx SPI Instance
1043 * @param Standard This parameter can be one of the following values:
1044 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1045 * @arg @ref LL_SPI_PROTOCOL_TI
1046 * @retval None
1047 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1048 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1049 {
1050 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1051 }
1052
1053 /**
1054 * @brief Get Serial protocol used
1055 * @rmtoll CFG2 SP LL_SPI_GetStandard
1056 * @param SPIx SPI Instance
1057 * @retval Returned value can be one of the following values:
1058 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1059 * @arg @ref LL_SPI_PROTOCOL_TI
1060 */
LL_SPI_GetStandard(const SPI_TypeDef * SPIx)1061 __STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
1062 {
1063 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1064 }
1065
1066 /**
1067 * @brief Set Clock phase
1068 * @note This configuration can not be changed when SPI is enabled.
1069 * This bit is not used in SPI TI mode.
1070 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1071 * @param SPIx SPI Instance
1072 * @param ClockPhase This parameter can be one of the following values:
1073 * @arg @ref LL_SPI_PHASE_1EDGE
1074 * @arg @ref LL_SPI_PHASE_2EDGE
1075 * @retval None
1076 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)1077 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1078 {
1079 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1080 }
1081
1082 /**
1083 * @brief Get Clock phase
1084 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1085 * @param SPIx SPI Instance
1086 * @retval Returned value can be one of the following values:
1087 * @arg @ref LL_SPI_PHASE_1EDGE
1088 * @arg @ref LL_SPI_PHASE_2EDGE
1089 */
LL_SPI_GetClockPhase(const SPI_TypeDef * SPIx)1090 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
1091 {
1092 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1093 }
1094
1095 /**
1096 * @brief Set Clock polarity
1097 * @note This configuration can not be changed when SPI is enabled.
1098 * This bit is not used in SPI TI mode.
1099 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1100 * @param SPIx SPI Instance
1101 * @param ClockPolarity This parameter can be one of the following values:
1102 * @arg @ref LL_SPI_POLARITY_LOW
1103 * @arg @ref LL_SPI_POLARITY_HIGH
1104 * @retval None
1105 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1106 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1107 {
1108 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1109 }
1110
1111 /**
1112 * @brief Get Clock polarity
1113 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1114 * @param SPIx SPI Instance
1115 * @retval Returned value can be one of the following values:
1116 * @arg @ref LL_SPI_POLARITY_LOW
1117 * @arg @ref LL_SPI_POLARITY_HIGH
1118 */
LL_SPI_GetClockPolarity(const SPI_TypeDef * SPIx)1119 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
1120 {
1121 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1122 }
1123
1124 /**
1125 * @brief Set NSS polarity
1126 * @note This configuration can not be changed when SPI is enabled.
1127 * This bit is not used in SPI TI mode.
1128 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1129 * @param SPIx SPI Instance
1130 * @param NSSPolarity This parameter can be one of the following values:
1131 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1132 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1133 * @retval None
1134 */
LL_SPI_SetNSSPolarity(SPI_TypeDef * SPIx,uint32_t NSSPolarity)1135 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1136 {
1137 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1138 }
1139
1140 /**
1141 * @brief Get NSS polarity
1142 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1143 * @param SPIx SPI Instance
1144 * @retval Returned value can be one of the following values:
1145 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1146 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1147 */
LL_SPI_GetNSSPolarity(const SPI_TypeDef * SPIx)1148 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
1149 {
1150 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1151 }
1152
1153 /**
1154 * @brief Set Baudrate Prescaler
1155 * @note This configuration can not be changed when SPI is enabled.
1156 * SPI BaudRate = fPCLK/Pescaler.
1157 * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n
1158 * CFG1 BPASS LL_SPI_SetBaudRatePrescaler
1159 * @param SPIx SPI Instance
1160 * @param Baudrate This parameter can be one of the following values:
1161 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1162 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1163 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1164 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1165 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1166 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1167 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1168 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1169 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1170 * @retval None
1171 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t Baudrate)1172 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1173 {
1174 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
1175 }
1176
1177 /**
1178 * @brief Get Baudrate Prescaler
1179 * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n
1180 * CFG1 BPASS LL_SPI_GetBaudRatePrescaler
1181 * @param SPIx SPI Instance
1182 * @retval Returned value can be one of the following values:
1183 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1184 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1185 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1186 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1187 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1188 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1189 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1190 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1191 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1192 */
LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef * SPIx)1193 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
1194 {
1195 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
1196 }
1197
1198 /**
1199 * @brief Set Transfer Bit Order
1200 * @note This configuration can not be changed when SPI is enabled.
1201 * This bit is not used in SPI TI mode.
1202 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1203 * @param SPIx SPI Instance
1204 * @param BitOrder This parameter can be one of the following values:
1205 * @arg @ref LL_SPI_LSB_FIRST
1206 * @arg @ref LL_SPI_MSB_FIRST
1207 * @retval None
1208 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)1209 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1210 {
1211 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1212 }
1213
1214 /**
1215 * @brief Get Transfer Bit Order
1216 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1217 * @param SPIx SPI Instance
1218 * @retval Returned value can be one of the following values:
1219 * @arg @ref LL_SPI_LSB_FIRST
1220 * @arg @ref LL_SPI_MSB_FIRST
1221 */
LL_SPI_GetTransferBitOrder(const SPI_TypeDef * SPIx)1222 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
1223 {
1224 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1225 }
1226
1227 /**
1228 * @brief Set Transfer Mode
1229 * @note This configuration can not be changed when SPI is enabled except for half duplex direction
1230 * using LL_SPI_SetHalfDuplexDirection.
1231 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1232 * CFG2 COMM LL_SPI_SetTransferDirection
1233 * @param SPIx SPI Instance
1234 * @param TransferDirection This parameter can be one of the following values:
1235 * @arg @ref LL_SPI_FULL_DUPLEX
1236 * @arg @ref LL_SPI_SIMPLEX_TX
1237 * @arg @ref LL_SPI_SIMPLEX_RX
1238 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1239 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1240 * @retval None
1241 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)1242 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1243 {
1244 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1245 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1246 }
1247
1248 /**
1249 * @brief Get Transfer Mode
1250 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1251 * CFG2 COMM LL_SPI_GetTransferDirection
1252 * @param SPIx SPI Instance
1253 * @retval Returned value can be one of the following values:
1254 * @arg @ref LL_SPI_FULL_DUPLEX
1255 * @arg @ref LL_SPI_SIMPLEX_TX
1256 * @arg @ref LL_SPI_SIMPLEX_RX
1257 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1258 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1259 */
LL_SPI_GetTransferDirection(const SPI_TypeDef * SPIx)1260 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
1261 {
1262 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1263 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1264 return (Hddir | Comm);
1265 }
1266
1267 /**
1268 * @brief Set direction for Half-Duplex Mode
1269 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1270 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1271 * @param SPIx SPI Instance
1272 * @param HalfDuplexDirection This parameter can be one of the following values:
1273 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1274 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1275 * @retval None
1276 */
LL_SPI_SetHalfDuplexDirection(SPI_TypeDef * SPIx,uint32_t HalfDuplexDirection)1277 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1278 {
1279 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1280 }
1281
1282 /**
1283 * @brief Get direction for Half-Duplex Mode
1284 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1285 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1286 * @param SPIx SPI Instance
1287 * @retval Returned value can be one of the following values:
1288 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1289 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1290 */
LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef * SPIx)1291 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
1292 {
1293 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1294 }
1295
1296 /**
1297 * @brief Set Frame Data Size
1298 * @note This configuration can not be changed when SPI is enabled.
1299 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1300 * @param SPIx SPI Instance
1301 * @param DataWidth This parameter can be one of the following values:
1302 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1303 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1304 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1305 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1306 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1307 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1308 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1309 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1310 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1311 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1312 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1313 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1314 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1315 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1316 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1317 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1318 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1319 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1320 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1321 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1322 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1323 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1324 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1325 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1326 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1327 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1328 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1329 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1330 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1331 * @retval None
1332 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)1333 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1334 {
1335 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1336 }
1337
1338 /**
1339 * @brief Get Frame Data Size
1340 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1341 * @param SPIx SPI Instance
1342 * @retval Returned value can be one of the following values:
1343 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1344 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1345 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1346 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1347 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1348 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1349 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1350 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1351 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1352 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1353 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1354 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1355 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1356 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1357 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1358 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1359 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1360 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1361 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1362 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1363 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1364 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1365 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1366 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1367 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1368 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1369 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1370 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1371 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1372 */
LL_SPI_GetDataWidth(const SPI_TypeDef * SPIx)1373 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
1374 {
1375 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1376 }
1377
1378 /**
1379 * @brief Set threshold of FIFO that triggers a transfer event
1380 * @note This configuration can not be changed when SPI is enabled.
1381 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1382 * @param SPIx SPI Instance
1383 * @param Threshold This parameter can be one of the following values:
1384 * @arg @ref LL_SPI_FIFO_TH_01DATA
1385 * @arg @ref LL_SPI_FIFO_TH_02DATA
1386 * @arg @ref LL_SPI_FIFO_TH_03DATA
1387 * @arg @ref LL_SPI_FIFO_TH_04DATA
1388 * @arg @ref LL_SPI_FIFO_TH_05DATA
1389 * @arg @ref LL_SPI_FIFO_TH_06DATA
1390 * @arg @ref LL_SPI_FIFO_TH_07DATA
1391 * @arg @ref LL_SPI_FIFO_TH_08DATA
1392 * @arg @ref LL_SPI_FIFO_TH_09DATA
1393 * @arg @ref LL_SPI_FIFO_TH_10DATA
1394 * @arg @ref LL_SPI_FIFO_TH_11DATA
1395 * @arg @ref LL_SPI_FIFO_TH_12DATA
1396 * @arg @ref LL_SPI_FIFO_TH_13DATA
1397 * @arg @ref LL_SPI_FIFO_TH_14DATA
1398 * @arg @ref LL_SPI_FIFO_TH_15DATA
1399 * @arg @ref LL_SPI_FIFO_TH_16DATA
1400 * @retval None
1401 */
LL_SPI_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)1402 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1403 {
1404 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1405 }
1406
1407 /**
1408 * @brief Get threshold of FIFO that triggers a transfer event
1409 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1410 * @param SPIx SPI Instance
1411 * @retval Returned value can be one of the following values:
1412 * @arg @ref LL_SPI_FIFO_TH_01DATA
1413 * @arg @ref LL_SPI_FIFO_TH_02DATA
1414 * @arg @ref LL_SPI_FIFO_TH_03DATA
1415 * @arg @ref LL_SPI_FIFO_TH_04DATA
1416 * @arg @ref LL_SPI_FIFO_TH_05DATA
1417 * @arg @ref LL_SPI_FIFO_TH_06DATA
1418 * @arg @ref LL_SPI_FIFO_TH_07DATA
1419 * @arg @ref LL_SPI_FIFO_TH_08DATA
1420 * @arg @ref LL_SPI_FIFO_TH_09DATA
1421 * @arg @ref LL_SPI_FIFO_TH_10DATA
1422 * @arg @ref LL_SPI_FIFO_TH_11DATA
1423 * @arg @ref LL_SPI_FIFO_TH_12DATA
1424 * @arg @ref LL_SPI_FIFO_TH_13DATA
1425 * @arg @ref LL_SPI_FIFO_TH_14DATA
1426 * @arg @ref LL_SPI_FIFO_TH_15DATA
1427 * @arg @ref LL_SPI_FIFO_TH_16DATA
1428 */
LL_SPI_GetFIFOThreshold(const SPI_TypeDef * SPIx)1429 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
1430 {
1431 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1432 }
1433
1434 /**
1435 * @brief Enable CRC
1436 * @note This configuration can not be changed when SPI is enabled.
1437 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1438 * @param SPIx SPI Instance
1439 * @retval None
1440 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)1441 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1442 {
1443 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1444 }
1445
1446 /**
1447 * @brief Disable CRC
1448 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1449 * @param SPIx SPI Instance
1450 * @retval None
1451 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)1452 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1453 {
1454 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1455 }
1456
1457 /**
1458 * @brief Check if CRC is enabled
1459 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1460 * @param SPIx SPI Instance
1461 * @retval State of bit (1 or 0).
1462 */
LL_SPI_IsEnabledCRC(const SPI_TypeDef * SPIx)1463 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
1464 {
1465 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1466 }
1467
1468 /**
1469 * @brief Set CRC Length
1470 * @note This configuration can not be changed when SPI is enabled.
1471 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1472 * @param SPIx SPI Instance
1473 * @param CRCLength This parameter can be one of the following values:
1474 * @arg @ref LL_SPI_CRC_4BIT
1475 * @arg @ref LL_SPI_CRC_5BIT
1476 * @arg @ref LL_SPI_CRC_6BIT
1477 * @arg @ref LL_SPI_CRC_7BIT
1478 * @arg @ref LL_SPI_CRC_8BIT
1479 * @arg @ref LL_SPI_CRC_9BIT
1480 * @arg @ref LL_SPI_CRC_10BIT
1481 * @arg @ref LL_SPI_CRC_11BIT
1482 * @arg @ref LL_SPI_CRC_12BIT
1483 * @arg @ref LL_SPI_CRC_13BIT
1484 * @arg @ref LL_SPI_CRC_14BIT
1485 * @arg @ref LL_SPI_CRC_15BIT
1486 * @arg @ref LL_SPI_CRC_16BIT
1487 * @arg @ref LL_SPI_CRC_17BIT
1488 * @arg @ref LL_SPI_CRC_18BIT
1489 * @arg @ref LL_SPI_CRC_19BIT
1490 * @arg @ref LL_SPI_CRC_20BIT
1491 * @arg @ref LL_SPI_CRC_21BIT
1492 * @arg @ref LL_SPI_CRC_22BIT
1493 * @arg @ref LL_SPI_CRC_23BIT
1494 * @arg @ref LL_SPI_CRC_24BIT
1495 * @arg @ref LL_SPI_CRC_25BIT
1496 * @arg @ref LL_SPI_CRC_26BIT
1497 * @arg @ref LL_SPI_CRC_27BIT
1498 * @arg @ref LL_SPI_CRC_28BIT
1499 * @arg @ref LL_SPI_CRC_29BIT
1500 * @arg @ref LL_SPI_CRC_30BIT
1501 * @arg @ref LL_SPI_CRC_31BIT
1502 * @arg @ref LL_SPI_CRC_32BIT
1503 * @retval None
1504 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)1505 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1506 {
1507 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1508 }
1509
1510 /**
1511 * @brief Get CRC Length
1512 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1513 * @param SPIx SPI Instance
1514 * @retval Returned value can be one of the following values:
1515 * @arg @ref LL_SPI_CRC_4BIT
1516 * @arg @ref LL_SPI_CRC_5BIT
1517 * @arg @ref LL_SPI_CRC_6BIT
1518 * @arg @ref LL_SPI_CRC_7BIT
1519 * @arg @ref LL_SPI_CRC_8BIT
1520 * @arg @ref LL_SPI_CRC_9BIT
1521 * @arg @ref LL_SPI_CRC_10BIT
1522 * @arg @ref LL_SPI_CRC_11BIT
1523 * @arg @ref LL_SPI_CRC_12BIT
1524 * @arg @ref LL_SPI_CRC_13BIT
1525 * @arg @ref LL_SPI_CRC_14BIT
1526 * @arg @ref LL_SPI_CRC_15BIT
1527 * @arg @ref LL_SPI_CRC_16BIT
1528 * @arg @ref LL_SPI_CRC_17BIT
1529 * @arg @ref LL_SPI_CRC_18BIT
1530 * @arg @ref LL_SPI_CRC_19BIT
1531 * @arg @ref LL_SPI_CRC_20BIT
1532 * @arg @ref LL_SPI_CRC_21BIT
1533 * @arg @ref LL_SPI_CRC_22BIT
1534 * @arg @ref LL_SPI_CRC_23BIT
1535 * @arg @ref LL_SPI_CRC_24BIT
1536 * @arg @ref LL_SPI_CRC_25BIT
1537 * @arg @ref LL_SPI_CRC_26BIT
1538 * @arg @ref LL_SPI_CRC_27BIT
1539 * @arg @ref LL_SPI_CRC_28BIT
1540 * @arg @ref LL_SPI_CRC_29BIT
1541 * @arg @ref LL_SPI_CRC_30BIT
1542 * @arg @ref LL_SPI_CRC_31BIT
1543 * @arg @ref LL_SPI_CRC_32BIT
1544 */
LL_SPI_GetCRCWidth(const SPI_TypeDef * SPIx)1545 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
1546 {
1547 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1548 }
1549
1550 /**
1551 * @brief Set NSS Mode
1552 * @note This configuration can not be changed when SPI is enabled.
1553 * This bit is not used in SPI TI mode.
1554 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1555 * CFG2 SSOE LL_SPI_SetNSSMode
1556 * @param SPIx SPI Instance
1557 * @param NSS This parameter can be one of the following values:
1558 * @arg @ref LL_SPI_NSS_SOFT
1559 * @arg @ref LL_SPI_NSS_HARD_INPUT
1560 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1561 * @retval None
1562 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)1563 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1564 {
1565 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1566 }
1567
1568 /**
1569 * @brief Set NSS Mode
1570 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1571 * CFG2 SSOE LL_SPI_GetNSSMode
1572 * @param SPIx SPI Instance
1573 * @retval Returned value can be one of the following values:
1574 * @arg @ref LL_SPI_NSS_SOFT
1575 * @arg @ref LL_SPI_NSS_HARD_INPUT
1576 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1577 */
LL_SPI_GetNSSMode(const SPI_TypeDef * SPIx)1578 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
1579 {
1580 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1581 }
1582
1583 /**
1584 * @brief Enable NSS pulse mgt
1585 * @note This configuration can not be changed when SPI is enabled.
1586 * This bit is not used in SPI TI mode.
1587 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1588 * @param SPIx SPI Instance
1589 * @retval None
1590 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)1591 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1592 {
1593 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1594 }
1595
1596 /**
1597 * @brief Disable NSS pulse mgt
1598 * @note This configuration can not be changed when SPI is enabled.
1599 * This bit is not used in SPI TI mode.
1600 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1601 * @param SPIx SPI Instance
1602 * @retval None
1603 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)1604 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1605 {
1606 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1607 }
1608
1609 /**
1610 * @brief Check if NSS pulse is enabled
1611 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1612 * @param SPIx SPI Instance
1613 * @retval State of bit (1 or 0)
1614 */
LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef * SPIx)1615 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
1616 {
1617 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1618 }
1619
1620 /**
1621 * @}
1622 */
1623
1624 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1625 * @{
1626 */
1627
1628 /**
1629 * @brief Check if there is enough data in FIFO to read a full packet
1630 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1631 * @param SPIx SPI Instance
1632 * @retval State of bit (1 or 0)
1633 */
LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef * SPIx)1634 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
1635 {
1636 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1637 }
1638
1639 /**
1640 * @brief Check if there is enough space in FIFO to hold a full packet
1641 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1642 * @param SPIx SPI Instance
1643 * @retval State of bit (1 or 0)
1644 */
LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef * SPIx)1645 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
1646 {
1647 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1648 }
1649
1650 /**
1651 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1652 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1653 * @param SPIx SPI Instance
1654 * @retval State of bit (1 or 0)
1655 */
LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef * SPIx)1656 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
1657 {
1658 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1659 }
1660
1661 /**
1662 * @brief Check that end of transfer event occurred
1663 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1664 * @param SPIx SPI Instance
1665 * @retval State of bit (1 or 0).
1666 */
LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef * SPIx)1667 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
1668 {
1669 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1670 }
1671
1672 /**
1673 * @brief Check that all required data has been filled in the fifo according to transfer size
1674 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1675 * @param SPIx SPI Instance
1676 * @retval State of bit (1 or 0).
1677 */
LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef * SPIx)1678 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
1679 {
1680 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1681 }
1682
1683 /**
1684 * @brief Get Underrun error flag
1685 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1686 * @param SPIx SPI Instance
1687 * @retval State of bit (1 or 0).
1688 */
LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef * SPIx)1689 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1690 {
1691 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1692 }
1693
1694 /**
1695 * @brief Get CRC error flag
1696 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1697 * @param SPIx SPI Instance
1698 * @retval State of bit (1 or 0).
1699 */
LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef * SPIx)1700 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
1701 {
1702 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1703 }
1704
1705 /**
1706 * @brief Get Mode fault error flag
1707 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1708 * @param SPIx SPI Instance
1709 * @retval State of bit (1 or 0).
1710 */
LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef * SPIx)1711 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
1712 {
1713 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1714 }
1715
1716 /**
1717 * @brief Get Overrun error flag
1718 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1719 * @param SPIx SPI Instance
1720 * @retval State of bit (1 or 0).
1721 */
LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)1722 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1723 {
1724 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1725 }
1726
1727 /**
1728 * @brief Get TI Frame format error flag
1729 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1730 * @param SPIx SPI Instance
1731 * @retval State of bit (1 or 0).
1732 */
LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)1733 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
1734 {
1735 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1736 }
1737
1738 /**
1739 * @brief Check if a suspend operation is done
1740 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1741 * @param SPIx SPI Instance
1742 * @retval State of bit (1 or 0)
1743 */
LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef * SPIx)1744 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
1745 {
1746 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1747 }
1748
1749 /**
1750 * @brief Check if last TxFIFO or CRC frame transmission is completed
1751 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1752 * @param SPIx SPI Instance
1753 * @retval State of bit (1 or 0).
1754 */
LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef * SPIx)1755 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
1756 {
1757 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1758 }
1759
1760 /**
1761 * @brief Check if at least one 32-bit data is available in RxFIFO
1762 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1763 * @param SPIx SPI Instance
1764 * @retval State of bit (1 or 0)
1765 */
LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef * SPIx)1766 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
1767 {
1768 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1769 }
1770
1771 /**
1772 * @brief Get number of data framed remaining in current TSIZE
1773 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1774 * @param SPIx SPI Instance
1775 * @retval 0..0xFFFF
1776 */
LL_SPI_GetRemainingDataFrames(const SPI_TypeDef * SPIx)1777 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
1778 {
1779 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1780 }
1781
1782 /**
1783 * @brief Get RxFIFO packing Level
1784 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1785 * @param SPIx SPI Instance
1786 * @retval Returned value can be one of the following values:
1787 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1788 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1789 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1790 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1791 */
LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef * SPIx)1792 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
1793 {
1794 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1795 }
1796
1797 /**
1798 * @brief Clear End Of Transfer flag
1799 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1800 * @param SPIx SPI Instance
1801 * @retval None
1802 */
LL_SPI_ClearFlag_EOT(SPI_TypeDef * SPIx)1803 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1804 {
1805 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1806 }
1807
1808 /**
1809 * @brief Clear TXTF flag
1810 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1811 * @param SPIx SPI Instance
1812 * @retval None
1813 */
LL_SPI_ClearFlag_TXTF(SPI_TypeDef * SPIx)1814 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1815 {
1816 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1817 }
1818
1819 /**
1820 * @brief Clear Underrun error flag
1821 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1822 * @param SPIx SPI Instance
1823 * @retval None
1824 */
LL_SPI_ClearFlag_UDR(SPI_TypeDef * SPIx)1825 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1826 {
1827 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1828 }
1829
1830 /**
1831 * @brief Clear Overrun error flag
1832 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1833 * @param SPIx SPI Instance
1834 * @retval None
1835 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1836 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1837 {
1838 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1839 }
1840
1841 /**
1842 * @brief Clear CRC error flag
1843 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1844 * @param SPIx SPI Instance
1845 * @retval None
1846 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1847 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1848 {
1849 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1850 }
1851
1852 /**
1853 * @brief Clear Mode fault error flag
1854 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1855 * @param SPIx SPI Instance
1856 * @retval None
1857 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1858 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1859 {
1860 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1861 }
1862
1863 /**
1864 * @brief Clear Frame format error flag
1865 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1866 * @param SPIx SPI Instance
1867 * @retval None
1868 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1869 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1870 {
1871 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1872 }
1873
1874 /**
1875 * @brief Clear SUSP flag
1876 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1877 * @param SPIx SPI Instance
1878 * @retval None
1879 */
LL_SPI_ClearFlag_SUSP(SPI_TypeDef * SPIx)1880 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1881 {
1882 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1883 }
1884
1885 /**
1886 * @}
1887 */
1888
1889 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1890 * @{
1891 */
1892
1893 /**
1894 * @brief Enable Rx Packet available IT
1895 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1896 * @param SPIx SPI Instance
1897 * @retval None
1898 */
LL_SPI_EnableIT_RXP(SPI_TypeDef * SPIx)1899 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1900 {
1901 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1902 }
1903
1904 /**
1905 * @brief Enable Tx Packet space available IT
1906 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1907 * @param SPIx SPI Instance
1908 * @retval None
1909 */
LL_SPI_EnableIT_TXP(SPI_TypeDef * SPIx)1910 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1911 {
1912 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
1913 }
1914
1915 /**
1916 * @brief Enable Duplex Packet available IT
1917 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
1918 * @param SPIx SPI Instance
1919 * @retval None
1920 */
LL_SPI_EnableIT_DXP(SPI_TypeDef * SPIx)1921 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
1922 {
1923 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
1924 }
1925
1926 /**
1927 * @brief Enable End Of Transfer IT
1928 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
1929 * @param SPIx SPI Instance
1930 * @retval None
1931 */
LL_SPI_EnableIT_EOT(SPI_TypeDef * SPIx)1932 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
1933 {
1934 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
1935 }
1936
1937 /**
1938 * @brief Enable TXTF IT
1939 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
1940 * @param SPIx SPI Instance
1941 * @retval None
1942 */
LL_SPI_EnableIT_TXTF(SPI_TypeDef * SPIx)1943 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
1944 {
1945 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
1946 }
1947
1948 /**
1949 * @brief Enable Underrun IT
1950 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
1951 * @param SPIx SPI Instance
1952 * @retval None
1953 */
LL_SPI_EnableIT_UDR(SPI_TypeDef * SPIx)1954 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
1955 {
1956 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
1957 }
1958
1959 /**
1960 * @brief Enable Overrun IT
1961 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
1962 * @param SPIx SPI Instance
1963 * @retval None
1964 */
LL_SPI_EnableIT_OVR(SPI_TypeDef * SPIx)1965 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
1966 {
1967 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
1968 }
1969
1970 /**
1971 * @brief Enable CRC Error IT
1972 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
1973 * @param SPIx SPI Instance
1974 * @retval None
1975 */
LL_SPI_EnableIT_CRCERR(SPI_TypeDef * SPIx)1976 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
1977 {
1978 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
1979 }
1980
1981 /**
1982 * @brief Enable TI Frame Format Error IT
1983 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
1984 * @param SPIx SPI Instance
1985 * @retval None
1986 */
LL_SPI_EnableIT_FRE(SPI_TypeDef * SPIx)1987 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
1988 {
1989 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
1990 }
1991
1992 /**
1993 * @brief Enable MODF IT
1994 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
1995 * @param SPIx SPI Instance
1996 * @retval None
1997 */
LL_SPI_EnableIT_MODF(SPI_TypeDef * SPIx)1998 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
1999 {
2000 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2001 }
2002
2003 /**
2004 * @brief Disable Rx Packet available IT
2005 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2006 * @param SPIx SPI Instance
2007 * @retval None
2008 */
LL_SPI_DisableIT_RXP(SPI_TypeDef * SPIx)2009 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2010 {
2011 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2012 }
2013
2014 /**
2015 * @brief Disable Tx Packet space available IT
2016 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2017 * @param SPIx SPI Instance
2018 * @retval None
2019 */
LL_SPI_DisableIT_TXP(SPI_TypeDef * SPIx)2020 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2021 {
2022 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2023 }
2024
2025 /**
2026 * @brief Disable Duplex Packet available IT
2027 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2028 * @param SPIx SPI Instance
2029 * @retval None
2030 */
LL_SPI_DisableIT_DXP(SPI_TypeDef * SPIx)2031 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2032 {
2033 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2034 }
2035
2036 /**
2037 * @brief Disable End Of Transfer IT
2038 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2039 * @param SPIx SPI Instance
2040 * @retval None
2041 */
LL_SPI_DisableIT_EOT(SPI_TypeDef * SPIx)2042 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2043 {
2044 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2045 }
2046
2047 /**
2048 * @brief Disable TXTF IT
2049 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2050 * @param SPIx SPI Instance
2051 * @retval None
2052 */
LL_SPI_DisableIT_TXTF(SPI_TypeDef * SPIx)2053 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2054 {
2055 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2056 }
2057
2058 /**
2059 * @brief Disable Underrun IT
2060 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2061 * @param SPIx SPI Instance
2062 * @retval None
2063 */
LL_SPI_DisableIT_UDR(SPI_TypeDef * SPIx)2064 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2065 {
2066 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2067 }
2068
2069 /**
2070 * @brief Disable Overrun IT
2071 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2072 * @param SPIx SPI Instance
2073 * @retval None
2074 */
LL_SPI_DisableIT_OVR(SPI_TypeDef * SPIx)2075 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2076 {
2077 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2078 }
2079
2080 /**
2081 * @brief Disable CRC Error IT
2082 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2083 * @param SPIx SPI Instance
2084 * @retval None
2085 */
LL_SPI_DisableIT_CRCERR(SPI_TypeDef * SPIx)2086 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2087 {
2088 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2089 }
2090
2091 /**
2092 * @brief Disable TI Frame Format Error IT
2093 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2094 * @param SPIx SPI Instance
2095 * @retval None
2096 */
LL_SPI_DisableIT_FRE(SPI_TypeDef * SPIx)2097 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2098 {
2099 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2100 }
2101
2102 /**
2103 * @brief Disable MODF IT
2104 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2105 * @param SPIx SPI Instance
2106 * @retval None
2107 */
LL_SPI_DisableIT_MODF(SPI_TypeDef * SPIx)2108 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2109 {
2110 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2111 }
2112
2113 /**
2114 * @brief Check if Rx Packet available IT is enabled
2115 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2116 * @param SPIx SPI Instance
2117 * @retval State of bit (1 or 0)
2118 */
LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef * SPIx)2119 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
2120 {
2121 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2122 }
2123
2124 /**
2125 * @brief Check if Tx Packet space available IT is enabled
2126 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2127 * @param SPIx SPI Instance
2128 * @retval State of bit (1 or 0)
2129 */
LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef * SPIx)2130 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
2131 {
2132 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2133 }
2134
2135 /**
2136 * @brief Check if Duplex Packet available IT is enabled
2137 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2138 * @param SPIx SPI Instance
2139 * @retval State of bit (1 or 0)
2140 */
LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef * SPIx)2141 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
2142 {
2143 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2144 }
2145
2146 /**
2147 * @brief Check if End Of Transfer IT is enabled
2148 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2149 * @param SPIx SPI Instance
2150 * @retval State of bit (1 or 0)
2151 */
LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef * SPIx)2152 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
2153 {
2154 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2155 }
2156
2157 /**
2158 * @brief Check if TXTF IT is enabled
2159 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2160 * @param SPIx SPI Instance
2161 * @retval State of bit (1 or 0)
2162 */
LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef * SPIx)2163 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
2164 {
2165 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2166 }
2167
2168 /**
2169 * @brief Check if Underrun IT is enabled
2170 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2171 * @param SPIx SPI Instance
2172 * @retval State of bit (1 or 0)
2173 */
LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef * SPIx)2174 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
2175 {
2176 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2177 }
2178
2179 /**
2180 * @brief Check if Overrun IT is enabled
2181 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2182 * @param SPIx SPI Instance
2183 * @retval State of bit (1 or 0)
2184 */
LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef * SPIx)2185 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
2186 {
2187 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2188 }
2189
2190 /**
2191 * @brief Check if CRC Error IT is enabled
2192 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2193 * @param SPIx SPI Instance
2194 * @retval State of bit (1 or 0)
2195 */
LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef * SPIx)2196 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
2197 {
2198 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2199 }
2200
2201 /**
2202 * @brief Check if TI Frame Format Error IT is enabled
2203 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2204 * @param SPIx SPI Instance
2205 * @retval State of bit (1 or 0)
2206 */
LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef * SPIx)2207 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
2208 {
2209 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2210 }
2211
2212 /**
2213 * @brief Check if MODF IT is enabled
2214 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2215 * @param SPIx SPI Instance
2216 * @retval State of bit (1 or 0)
2217 */
LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef * SPIx)2218 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
2219 {
2220 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2221 }
2222
2223 /**
2224 * @}
2225 */
2226
2227 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
2228 * @{
2229 */
2230
2231 /**
2232 * @brief Enable DMA Rx
2233 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2234 * @param SPIx SPI Instance
2235 * @retval None
2236 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)2237 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2238 {
2239 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2240 }
2241
2242 /**
2243 * @brief Disable DMA Rx
2244 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2245 * @param SPIx SPI Instance
2246 * @retval None
2247 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)2248 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2249 {
2250 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2251 }
2252
2253 /**
2254 * @brief Check if DMA Rx is enabled
2255 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2256 * @param SPIx SPI Instance
2257 * @retval State of bit (1 or 0)
2258 */
LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)2259 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
2260 {
2261 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2262 }
2263
2264 /**
2265 * @brief Enable DMA Tx
2266 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2267 * @param SPIx SPI Instance
2268 * @retval None
2269 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)2270 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2271 {
2272 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2273 }
2274
2275 /**
2276 * @brief Disable DMA Tx
2277 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2278 * @param SPIx SPI Instance
2279 * @retval None
2280 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)2281 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2282 {
2283 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2284 }
2285
2286 /**
2287 * @brief Check if DMA Tx is enabled
2288 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2289 * @param SPIx SPI Instance
2290 * @retval State of bit (1 or 0)
2291 */
LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)2292 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
2293 {
2294 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2295 }
2296 /**
2297 * @brief Get the data register address used for DMA transfer
2298 * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr
2299 * @param SPIx SPI Instance
2300 * @retval Address of data register
2301 */
LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef * SPIx)2302 __STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
2303 {
2304 return (uint32_t) &(SPIx->TXDR);
2305 }
2306
2307 /**
2308 * @brief Get the data register address used for DMA transfer
2309 * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr
2310 * @param SPIx SPI Instance
2311 * @retval Address of data register
2312 */
LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef * SPIx)2313 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
2314 {
2315 return (uint32_t) &(SPIx->RXDR);
2316 }
2317 /**
2318 * @}
2319 */
2320
2321 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2322 * @{
2323 */
2324
2325 /**
2326 * @brief Read Data Register
2327 * @rmtoll RXDR . LL_SPI_ReceiveData8
2328 * @param SPIx SPI Instance
2329 * @retval 0..0xFF
2330 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)2331 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2332 {
2333 return (*((__IO uint8_t *)&SPIx->RXDR));
2334 }
2335
2336 /**
2337 * @brief Read Data Register
2338 * @rmtoll RXDR . LL_SPI_ReceiveData16
2339 * @param SPIx SPI Instance
2340 * @retval 0..0xFFFF
2341 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)2342 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2343 {
2344 #if defined (__GNUC__)
2345 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2346 return (*spirxdr);
2347 #else
2348 return (*((__IO uint16_t *)&SPIx->RXDR));
2349 #endif /* __GNUC__ */
2350 }
2351
2352 /**
2353 * @brief Read Data Register
2354 * @rmtoll RXDR . LL_SPI_ReceiveData32
2355 * @param SPIx SPI Instance
2356 * @retval 0..0xFFFFFFFF
2357 */
LL_SPI_ReceiveData32(SPI_TypeDef * SPIx)2358 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2359 {
2360 return (*((__IO uint32_t *)&SPIx->RXDR));
2361 }
2362
2363 /**
2364 * @brief Write Data Register
2365 * @rmtoll TXDR . LL_SPI_TransmitData8
2366 * @param SPIx SPI Instance
2367 * @param TxData 0..0xFF
2368 * @retval None
2369 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)2370 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2371 {
2372 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2373 }
2374
2375 /**
2376 * @brief Write Data Register
2377 * @rmtoll TXDR . LL_SPI_TransmitData16
2378 * @param SPIx SPI Instance
2379 * @param TxData 0..0xFFFF
2380 * @retval None
2381 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)2382 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2383 {
2384 #if defined (__GNUC__)
2385 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2386 *spitxdr = TxData;
2387 #else
2388 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2389 #endif /* __GNUC__ */
2390 }
2391
2392 /**
2393 * @brief Write Data Register
2394 * @rmtoll TXDR . LL_SPI_TransmitData32
2395 * @param SPIx SPI Instance
2396 * @param TxData 0..0xFFFFFFFF
2397 * @retval None
2398 */
LL_SPI_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)2399 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2400 {
2401 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2402 }
2403
2404 /**
2405 * @brief Set polynomial for CRC calcul
2406 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2407 * @param SPIx SPI Instance
2408 * @param CRCPoly 0..0xFFFFFFFF
2409 * @retval None
2410 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)2411 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2412 {
2413 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2414 }
2415
2416 /**
2417 * @brief Get polynomial for CRC calcul
2418 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2419 * @param SPIx SPI Instance
2420 * @retval 0..0xFFFFFFFF
2421 */
LL_SPI_GetCRCPolynomial(const SPI_TypeDef * SPIx)2422 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
2423 {
2424 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2425 }
2426
2427 /**
2428 * @brief Set the underrun pattern
2429 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2430 * @param SPIx SPI Instance
2431 * @param Pattern 0..0xFFFFFFFF
2432 * @retval None
2433 */
LL_SPI_SetUDRPattern(SPI_TypeDef * SPIx,uint32_t Pattern)2434 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2435 {
2436 WRITE_REG(SPIx->UDRDR, Pattern);
2437 }
2438
2439 /**
2440 * @brief Get the underrun pattern
2441 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2442 * @param SPIx SPI Instance
2443 * @retval 0..0xFFFFFFFF
2444 */
LL_SPI_GetUDRPattern(const SPI_TypeDef * SPIx)2445 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
2446 {
2447 return (uint32_t)(READ_REG(SPIx->UDRDR));
2448 }
2449
2450 /**
2451 * @brief Get Rx CRC
2452 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2453 * @param SPIx SPI Instance
2454 * @retval 0..0xFFFFFFFF
2455 */
LL_SPI_GetRxCRC(const SPI_TypeDef * SPIx)2456 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
2457 {
2458 return (uint32_t)(READ_REG(SPIx->RXCRC));
2459 }
2460
2461 /**
2462 * @brief Get Tx CRC
2463 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2464 * @param SPIx SPI Instance
2465 * @retval 0..0xFFFFFFFF
2466 */
LL_SPI_GetTxCRC(const SPI_TypeDef * SPIx)2467 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
2468 {
2469 return (uint32_t)(READ_REG(SPIx->TXCRC));
2470 }
2471
2472 /**
2473 * @}
2474 */
2475
2476 #if defined(USE_FULL_LL_DRIVER)
2477 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2478 * @{
2479 */
2480
2481 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
2482 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2483 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2484
2485 /**
2486 * @}
2487 */
2488 #endif /* USE_FULL_LL_DRIVER */
2489 /**
2490 * @}
2491 */
2492 /**
2493 * @}
2494 */
2495
2496 /** @defgroup I2S_LL I2S
2497 * @{
2498 */
2499
2500 /* Private variables ---------------------------------------------------------*/
2501 /* Private constants ---------------------------------------------------------*/
2502 /* Private macros ------------------------------------------------------------*/
2503
2504 /* Exported types ------------------------------------------------------------*/
2505 #if defined(USE_FULL_LL_DRIVER)
2506 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
2507 * @{
2508 */
2509
2510 /**
2511 * @brief I2S Init structure definition
2512 */
2513
2514 typedef struct
2515 {
2516 uint32_t Mode; /*!< Specifies the I2S operating mode.
2517 This parameter can be a value of @ref I2S_LL_EC_MODE
2518
2519 This feature can be modified afterwards using unitary function
2520 @ref LL_I2S_SetTransferMode().*/
2521
2522 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
2523 This parameter can be a value of @ref I2S_LL_EC_STANDARD
2524
2525 This feature can be modified afterwards using unitary function
2526 @ref LL_I2S_SetStandard().*/
2527
2528
2529 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
2530 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
2531
2532 This feature can be modified afterwards using unitary function
2533 @ref LL_I2S_SetDataFormat().*/
2534
2535
2536 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
2537 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
2538
2539 This feature can be modified afterwards using unitary functions
2540 @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
2541
2542
2543 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
2544 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
2545
2546 Audio Frequency can be modified afterwards using Reference manual formulas
2547 to calculate Prescaler Linear, Parity and unitary functions
2548 @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity()
2549 to set it.*/
2550
2551
2552 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
2553 This parameter can be a value of @ref I2S_LL_EC_POLARITY
2554
2555 This feature can be modified afterwards using unitary function
2556 @ref LL_I2S_SetClockPolarity().*/
2557
2558 } LL_I2S_InitTypeDef;
2559
2560 /**
2561 * @}
2562 */
2563 #endif /*USE_FULL_LL_DRIVER*/
2564
2565 /* Exported constants --------------------------------------------------------*/
2566 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
2567 * @{
2568 */
2569
2570 /** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
2571 * @{
2572 */
2573 #define LL_I2S_DATAFORMAT_16B (0x00000000UL)
2574 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
2575 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
2576 #define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
2577 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
2578 /**
2579 * @}
2580 */
2581
2582 /** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
2583 * @{
2584 */
2585 #define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
2586 #define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
2587 /**
2588 * @}
2589 */
2590
2591 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
2592 * @{
2593 */
2594 #define LL_I2S_POLARITY_LOW (0x00000000UL)
2595 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
2596 /**
2597 * @}
2598 */
2599
2600 /** @defgroup I2S_LL_EC_STANDARD I2S Standard
2601 * @{
2602 */
2603 #define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
2604 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
2605 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
2606 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
2607 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
2608 /**
2609 * @}
2610 */
2611
2612 /** @defgroup I2S_LL_EC_MODE Operation Mode
2613 * @{
2614 */
2615 #define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
2616 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
2617 #define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
2618 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
2619 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
2620 #define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
2621 /**
2622 * @}
2623 */
2624
2625 /** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
2626 * @{
2627 */
2628 #define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
2629 #define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
2630 /**
2631 * @}
2632 */
2633
2634 /** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
2635 * @{
2636 */
2637 #define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
2638 #define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
2639 #define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
2640 #define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
2641 #define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
2642 #define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
2643 #define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
2644 #define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
2645 /**
2646 * @}
2647 */
2648
2649 /** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
2650 * @{
2651 */
2652 #define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
2653 #define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
2654 /**
2655 * @}
2656 */
2657
2658 #if defined(USE_FULL_LL_DRIVER)
2659
2660 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
2661 * @{
2662 */
2663 #define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
2664 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
2665 /**
2666 * @}
2667 */
2668
2669 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
2670 * @{
2671 */
2672
2673 #define LL_I2S_AUDIOFREQ_192K 192000UL /*!< Audio Frequency configuration 192000 Hz */
2674 #define LL_I2S_AUDIOFREQ_96K 96000UL /*!< Audio Frequency configuration 96000 Hz */
2675 #define LL_I2S_AUDIOFREQ_48K 48000UL /*!< Audio Frequency configuration 48000 Hz */
2676 #define LL_I2S_AUDIOFREQ_44K 44100UL /*!< Audio Frequency configuration 44100 Hz */
2677 #define LL_I2S_AUDIOFREQ_32K 32000UL /*!< Audio Frequency configuration 32000 Hz */
2678 #define LL_I2S_AUDIOFREQ_22K 22050UL /*!< Audio Frequency configuration 22050 Hz */
2679 #define LL_I2S_AUDIOFREQ_16K 16000UL /*!< Audio Frequency configuration 16000 Hz */
2680 #define LL_I2S_AUDIOFREQ_11K 11025UL /*!< Audio Frequency configuration 11025 Hz */
2681 #define LL_I2S_AUDIOFREQ_8K 8000UL /*!< Audio Frequency configuration 8000 Hz */
2682 #define LL_I2S_AUDIOFREQ_DEFAULT 0UL /*!< Audio Freq not specified. Register I2SDIV = 0 */
2683 /**
2684 * @}
2685 */
2686 #endif /* USE_FULL_LL_DRIVER */
2687
2688 /**
2689 * @}
2690 */
2691
2692 /* Exported macro ------------------------------------------------------------*/
2693 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
2694 * @{
2695 */
2696
2697 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
2698 * @{
2699 */
2700
2701 /**
2702 * @brief Write a value in I2S register
2703 * @param __INSTANCE__ I2S Instance
2704 * @param __REG__ Register to be written
2705 * @param __VALUE__ Value to be written in the register
2706 * @retval None
2707 */
2708 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2709
2710 /**
2711 * @brief Read a value in I2S register
2712 * @param __INSTANCE__ I2S Instance
2713 * @param __REG__ Register to be read
2714 * @retval Register value
2715 */
2716 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2717 /**
2718 * @}
2719 */
2720
2721 /**
2722 * @}
2723 */
2724
2725
2726 /* Exported functions --------------------------------------------------------*/
2727
2728 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
2729 * @{
2730 */
2731
2732 /** @defgroup I2S_LL_EF_Configuration Configuration
2733 * @{
2734 */
2735
2736 /**
2737 * @brief Set I2S Data frame format
2738 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
2739 * I2SCFGR CHLEN LL_I2S_SetDataFormat\n
2740 * I2SCFGR DATFMT LL_I2S_SetDataFormat
2741 * @param SPIx SPI Handle
2742 * @param DataLength This parameter can be one of the following values:
2743 * @arg @ref LL_I2S_DATAFORMAT_16B
2744 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2745 * @arg @ref LL_I2S_DATAFORMAT_24B
2746 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2747 * @arg @ref LL_I2S_DATAFORMAT_32B
2748 * @retval None
2749 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataLength)2750 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
2751 {
2752 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
2753 }
2754
2755 /**
2756 * @brief Get I2S Data frame format
2757 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
2758 * I2SCFGR CHLEN LL_I2S_GetDataFormat\n
2759 * I2SCFGR DATFMT LL_I2S_GetDataFormat
2760 * @param SPIx SPI Handle
2761 * @retval Return value can be one of the following values:
2762 * @arg @ref LL_I2S_DATAFORMAT_16B
2763 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2764 * @arg @ref LL_I2S_DATAFORMAT_24B
2765 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2766 * @arg @ref LL_I2S_DATAFORMAT_32B
2767 */
LL_I2S_GetDataFormat(const SPI_TypeDef * SPIx)2768 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
2769 {
2770 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
2771 }
2772
2773 /**
2774 * @brief Set I2S Channel Length Type
2775 * @note This feature is useful with SLAVE only
2776 * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType
2777 * @param SPIx SPI Handle
2778 * @param ChannelLengthType This parameter can be one of the following values:
2779 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2780 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2781 * @retval None
2782 */
LL_I2S_SetChannelLengthType(SPI_TypeDef * SPIx,uint32_t ChannelLengthType)2783 __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
2784 {
2785 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
2786 }
2787
2788 /**
2789 * @brief Get I2S Channel Length Type
2790 * @note This feature is useful with SLAVE only
2791 * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType
2792 * @param SPIx SPI Handle
2793 * @retval Return value can be one of the following values:
2794 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2795 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2796 */
LL_I2S_GetChannelLengthType(const SPI_TypeDef * SPIx)2797 __STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(const SPI_TypeDef *SPIx)
2798 {
2799 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
2800 }
2801
2802 /**
2803 * @brief Invert the default polarity of WS signal
2804 * @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion
2805 * @param SPIx SPI Handle
2806 * @retval None
2807 */
LL_I2S_EnableWordSelectInversion(SPI_TypeDef * SPIx)2808 __STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
2809 {
2810 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2811 }
2812
2813 /**
2814 * @brief Use the default polarity of WS signal
2815 * @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion
2816 * @param SPIx SPI Handle
2817 * @retval None
2818 */
LL_I2S_DisableWordSelectInversion(SPI_TypeDef * SPIx)2819 __STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
2820 {
2821 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2822 }
2823
2824 /**
2825 * @brief Check if polarity of WS signal is inverted
2826 * @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion
2827 * @param SPIx SPI Handle
2828 * @retval State of bit (1 or 0)
2829 */
LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef * SPIx)2830 __STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef *SPIx)
2831 {
2832 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
2833 }
2834
2835 /**
2836 * @brief Set 2S Clock Polarity
2837 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
2838 * @param SPIx SPI Handle
2839 * @param ClockPolarity This parameter can be one of the following values:
2840 * @arg @ref LL_I2S_POLARITY_LOW
2841 * @arg @ref LL_I2S_POLARITY_HIGH
2842 * @retval None
2843 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)2844 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
2845 {
2846 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
2847 }
2848
2849 /**
2850 * @brief Get 2S Clock Polarity
2851 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
2852 * @param SPIx SPI Handle
2853 * @retval Return value can be one of the following values:
2854 * @arg @ref LL_I2S_POLARITY_LOW
2855 * @arg @ref LL_I2S_POLARITY_HIGH
2856 */
LL_I2S_GetClockPolarity(const SPI_TypeDef * SPIx)2857 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
2858 {
2859 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
2860 }
2861
2862 /**
2863 * @brief Set I2S standard
2864 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
2865 * I2SCFGR PCMSYNC LL_I2S_SetStandard
2866 * @param SPIx SPI Handle
2867 * @param Standard This parameter can be one of the following values:
2868 * @arg @ref LL_I2S_STANDARD_PHILIPS
2869 * @arg @ref LL_I2S_STANDARD_MSB
2870 * @arg @ref LL_I2S_STANDARD_LSB
2871 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2872 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2873 * @retval None
2874 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)2875 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
2876 {
2877 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
2878 }
2879
2880 /**
2881 * @brief Get I2S standard
2882 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
2883 * I2SCFGR PCMSYNC LL_I2S_GetStandard
2884 * @param SPIx SPI Handle
2885 * @retval Return value can be one of the following values:
2886 * @arg @ref LL_I2S_STANDARD_PHILIPS
2887 * @arg @ref LL_I2S_STANDARD_MSB
2888 * @arg @ref LL_I2S_STANDARD_LSB
2889 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2890 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2891 */
LL_I2S_GetStandard(const SPI_TypeDef * SPIx)2892 __STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
2893 {
2894 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
2895 }
2896
2897 /**
2898 * @brief Set I2S config
2899 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
2900 * @param SPIx SPI Handle
2901 * @param Standard This parameter can be one of the following values:
2902 * @arg @ref LL_I2S_MODE_SLAVE_TX
2903 * @arg @ref LL_I2S_MODE_SLAVE_RX
2904 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
2905 * @arg @ref LL_I2S_MODE_MASTER_TX
2906 * @arg @ref LL_I2S_MODE_MASTER_RX
2907 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
2908 * @retval None
2909 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Standard)2910 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
2911 {
2912 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
2913 }
2914
2915 /**
2916 * @brief Get I2S config
2917 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
2918 * @param SPIx SPI Handle
2919 * @retval Return value can be one of the following values:
2920 * @arg @ref LL_I2S_MODE_SLAVE_TX
2921 * @arg @ref LL_I2S_MODE_SLAVE_RX
2922 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
2923 * @arg @ref LL_I2S_MODE_MASTER_TX
2924 * @arg @ref LL_I2S_MODE_MASTER_RX
2925 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
2926 */
LL_I2S_GetTransferMode(const SPI_TypeDef * SPIx)2927 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
2928 {
2929 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
2930 }
2931
2932 /**
2933 * @brief Select I2S mode and Enable I2S peripheral
2934 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
2935 * CR1 SPE LL_I2S_Enable
2936 * @param SPIx SPI Handle
2937 * @retval None
2938 */
LL_I2S_Enable(SPI_TypeDef * SPIx)2939 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
2940 {
2941 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
2942 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
2943 }
2944
2945 /**
2946 * @brief Disable I2S peripheral and disable I2S mode
2947 * @rmtoll CR1 SPE LL_I2S_Disable\n
2948 * I2SCFGR I2SMOD LL_I2S_Disable
2949 * @param SPIx SPI Handle
2950 * @retval None
2951 */
LL_I2S_Disable(SPI_TypeDef * SPIx)2952 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
2953 {
2954 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
2955 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
2956 }
2957
2958 /**
2959 * @brief Swap the SDO and SDI pin
2960 * @note This configuration can not be changed when I2S is enabled.
2961 * @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap
2962 * @param SPIx SPI Instance
2963 * @retval None
2964 */
LL_I2S_EnableIOSwap(SPI_TypeDef * SPIx)2965 __STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
2966 {
2967 LL_SPI_EnableIOSwap(SPIx);
2968 }
2969
2970 /**
2971 * @brief Restore default function for SDO and SDI pin
2972 * @note This configuration can not be changed when I2S is enabled.
2973 * @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap
2974 * @param SPIx SPI Instance
2975 * @retval None
2976 */
LL_I2S_DisableIOSwap(SPI_TypeDef * SPIx)2977 __STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
2978 {
2979 LL_SPI_DisableIOSwap(SPIx);
2980 }
2981
2982 /**
2983 * @brief Check if SDO and SDI pin are swapped
2984 * @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap
2985 * @param SPIx SPI Instance
2986 * @retval State of bit (1 or 0)
2987 */
LL_I2S_IsEnabledIOSwap(const SPI_TypeDef * SPIx)2988 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
2989 {
2990 return LL_SPI_IsEnabledIOSwap(SPIx);
2991 }
2992
2993 /**
2994 * @brief Enable GPIO control
2995 * @note This configuration can not be changed when I2S is enabled.
2996 * @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl
2997 * @param SPIx SPI Instance
2998 * @retval None
2999 */
LL_I2S_EnableGPIOControl(SPI_TypeDef * SPIx)3000 __STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
3001 {
3002 LL_SPI_EnableGPIOControl(SPIx);
3003 }
3004
3005 /**
3006 * @brief Disable GPIO control
3007 * @note This configuration can not be changed when I2S is enabled.
3008 * @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl
3009 * @param SPIx SPI Instance
3010 * @retval None
3011 */
LL_I2S_DisableGPIOControl(SPI_TypeDef * SPIx)3012 __STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
3013 {
3014 LL_SPI_DisableGPIOControl(SPIx);
3015 }
3016
3017 /**
3018 * @brief Check if GPIO control is active
3019 * @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl
3020 * @param SPIx SPI Instance
3021 * @retval State of bit (1 or 0)
3022 */
LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef * SPIx)3023 __STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
3024 {
3025 return LL_SPI_IsEnabledGPIOControl(SPIx);
3026 }
3027
3028 /**
3029 * @brief Lock the AF configuration of associated IOs
3030 * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
3031 * The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
3032 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
3033 * @param SPIx SPI Instance
3034 * @retval None
3035 */
LL_I2S_EnableIOLock(SPI_TypeDef * SPIx)3036 __STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
3037 {
3038 LL_SPI_EnableIOLock(SPIx);
3039 }
3040
3041 /**
3042 * @brief Check if the the SPI_CFG2 register is locked
3043 * @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock
3044 * @param SPIx SPI Instance
3045 * @retval State of bit (1 or 0)
3046 */
LL_I2S_IsEnabledIOLock(const SPI_TypeDef * SPIx)3047 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(const SPI_TypeDef *SPIx)
3048 {
3049 return LL_SPI_IsEnabledIOLock(SPIx);
3050 }
3051
3052 /**
3053 * @brief Set Transfer Bit Order
3054 * @note This configuration can not be changed when I2S is enabled.
3055 * @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder
3056 * @param SPIx SPI Instance
3057 * @param BitOrder This parameter can be one of the following values:
3058 * @arg @ref LL_I2S_LSB_FIRST
3059 * @arg @ref LL_I2S_MSB_FIRST
3060 * @retval None
3061 */
LL_I2S_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)3062 __STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
3063 {
3064 LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
3065 }
3066 /**
3067 * @brief Get Transfer Bit Order
3068 * @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder
3069 * @param SPIx SPI Instance
3070 * @retval Returned value can be one of the following values:
3071 * @arg @ref LL_I2S_LSB_FIRST
3072 * @arg @ref LL_I2S_MSB_FIRST
3073 */
LL_I2S_GetTransferBitOrder(const SPI_TypeDef * SPIx)3074 __STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(const SPI_TypeDef *SPIx)
3075 {
3076 return LL_SPI_GetTransferBitOrder(SPIx);
3077 }
3078
3079 /**
3080 * @brief Start effective transfer on wire
3081 * @rmtoll CR1 CSTART LL_I2S_StartTransfer
3082 * @param SPIx SPI Instance
3083 * @retval None
3084 */
LL_I2S_StartTransfer(SPI_TypeDef * SPIx)3085 __STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
3086 {
3087 LL_SPI_StartMasterTransfer(SPIx);
3088 }
3089
3090 /**
3091 * @brief Check if there is an unfinished transfer
3092 * @rmtoll CR1 CSTART LL_I2S_IsActiveTransfer
3093 * @param SPIx SPI Instance
3094 * @retval State of bit (1 or 0)
3095 */
LL_I2S_IsActiveTransfer(const SPI_TypeDef * SPIx)3096 __STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(const SPI_TypeDef *SPIx)
3097 {
3098 return LL_SPI_IsActiveMasterTransfer(SPIx);
3099 }
3100
3101 /**
3102 * @brief Set threshold of FIFO that triggers a transfer event
3103 * @note This configuration can not be changed when I2S is enabled.
3104 * @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold
3105 * @param SPIx SPI Instance
3106 * @param Threshold This parameter can be one of the following values:
3107 * @arg @ref LL_I2S_FIFO_TH_01DATA
3108 * @arg @ref LL_I2S_FIFO_TH_02DATA
3109 * @arg @ref LL_I2S_FIFO_TH_03DATA
3110 * @arg @ref LL_I2S_FIFO_TH_04DATA
3111 * @arg @ref LL_I2S_FIFO_TH_05DATA
3112 * @arg @ref LL_I2S_FIFO_TH_06DATA
3113 * @arg @ref LL_I2S_FIFO_TH_07DATA
3114 * @arg @ref LL_I2S_FIFO_TH_08DATA
3115 * @retval None
3116 */
LL_I2S_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)3117 __STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
3118 {
3119 LL_SPI_SetFIFOThreshold(SPIx, Threshold);
3120 }
3121
3122 /**
3123 * @brief Get threshold of FIFO that triggers a transfer event
3124 * @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold
3125 * @param SPIx SPI Instance
3126 * @retval Returned value can be one of the following values:
3127 * @arg @ref LL_I2S_FIFO_TH_01DATA
3128 * @arg @ref LL_I2S_FIFO_TH_02DATA
3129 * @arg @ref LL_I2S_FIFO_TH_03DATA
3130 * @arg @ref LL_I2S_FIFO_TH_04DATA
3131 * @arg @ref LL_I2S_FIFO_TH_05DATA
3132 * @arg @ref LL_I2S_FIFO_TH_06DATA
3133 * @arg @ref LL_I2S_FIFO_TH_07DATA
3134 * @arg @ref LL_I2S_FIFO_TH_08DATA
3135 */
LL_I2S_GetFIFOThreshold(const SPI_TypeDef * SPIx)3136 __STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(const SPI_TypeDef *SPIx)
3137 {
3138 return LL_SPI_GetFIFOThreshold(SPIx);
3139 }
3140
3141 /**
3142 * @brief Set I2S linear prescaler
3143 * @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear
3144 * @param SPIx SPI Instance
3145 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3146 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
3147 * @retval None
3148 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint32_t PrescalerLinear)3149 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
3150 {
3151 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
3152 }
3153
3154 /**
3155 * @brief Get I2S linear prescaler
3156 * @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear
3157 * @param SPIx SPI Instance
3158 * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3159 */
LL_I2S_GetPrescalerLinear(const SPI_TypeDef * SPIx)3160 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
3161 {
3162 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
3163 }
3164
3165 /**
3166 * @brief Set I2S parity prescaler
3167 * @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity
3168 * @param SPIx SPI Instance
3169 * @param PrescalerParity This parameter can be one of the following values:
3170 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3171 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3172 * @retval None
3173 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)3174 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
3175 {
3176 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
3177 }
3178
3179 /**
3180 * @brief Get I2S parity prescaler
3181 * @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity
3182 * @param SPIx SPI Instance
3183 * @retval Returned value can be one of the following values:
3184 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3185 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3186 */
LL_I2S_GetPrescalerParity(const SPI_TypeDef * SPIx)3187 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
3188 {
3189 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
3190 }
3191
3192 /**
3193 * @brief Enable the Master Clock Output (Pin MCK)
3194 * @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock
3195 * @param SPIx SPI Handle
3196 * @retval None
3197 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)3198 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
3199 {
3200 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3201 }
3202
3203 /**
3204 * @brief Disable the Master Clock Output (Pin MCK)
3205 * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock
3206 * @param SPIx SPI Handle
3207 * @retval None
3208 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)3209 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
3210 {
3211 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3212 }
3213
3214 /**
3215 * @brief Check if the master clock output (Pin MCK) is enabled
3216 * @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock
3217 * @param SPIx SPI Instance
3218 * @retval State of bit (1 or 0)
3219 */
LL_I2S_IsEnabledMasterClock(const SPI_TypeDef * SPIx)3220 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
3221 {
3222 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
3223 }
3224
3225 /**
3226 * @}
3227 */
3228
3229
3230 /** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
3231 * @{
3232 */
3233
3234 /**
3235 * @brief Check if there enough data in FIFO to read a full packet
3236 * @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP
3237 * @param SPIx SPI Instance
3238 * @retval State of bit (1 or 0)
3239 */
LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef * SPIx)3240 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
3241 {
3242 return LL_SPI_IsActiveFlag_RXP(SPIx);
3243 }
3244
3245 /**
3246 * @brief Check if there enough space in FIFO to hold a full packet
3247 * @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP
3248 * @param SPIx SPI Instance
3249 * @retval State of bit (1 or 0)
3250 */
LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef * SPIx)3251 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
3252 {
3253 return LL_SPI_IsActiveFlag_TXP(SPIx);
3254 }
3255
3256 /**
3257 * @brief Get Underrun error flag
3258 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
3259 * @param SPIx SPI Instance
3260 * @retval State of bit (1 or 0)
3261 */
LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef * SPIx)3262 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
3263 {
3264 return LL_SPI_IsActiveFlag_UDR(SPIx);
3265 }
3266
3267 /**
3268 * @brief Get Overrun error flag
3269 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
3270 * @param SPIx SPI Instance
3271 * @retval State of bit (1 or 0).
3272 */
LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)3273 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
3274 {
3275 return LL_SPI_IsActiveFlag_OVR(SPIx);
3276 }
3277
3278 /**
3279 * @brief Get TI Frame format error flag
3280 * @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE
3281 * @param SPIx SPI Instance
3282 * @retval State of bit (1 or 0).
3283 */
LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)3284 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
3285 {
3286 return LL_SPI_IsActiveFlag_FRE(SPIx);
3287 }
3288
3289 /**
3290 * @brief Clear Underrun error flag
3291 * @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR
3292 * @param SPIx SPI Instance
3293 * @retval None
3294 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)3295 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
3296 {
3297 LL_SPI_ClearFlag_UDR(SPIx);
3298 }
3299
3300 /**
3301 * @brief Clear Overrun error flag
3302 * @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR
3303 * @param SPIx SPI Instance
3304 * @retval None
3305 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)3306 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
3307 {
3308 LL_SPI_ClearFlag_OVR(SPIx);
3309 }
3310
3311 /**
3312 * @brief Clear Frame format error flag
3313 * @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE
3314 * @param SPIx SPI Instance
3315 * @retval None
3316 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)3317 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
3318 {
3319 LL_SPI_ClearFlag_FRE(SPIx);
3320 }
3321
3322 /**
3323 * @}
3324 */
3325
3326 /** @defgroup I2S_LL_EF_IT_Management IT_Management
3327 * @{
3328 */
3329
3330 /**
3331 * @brief Enable Rx Packet available IT
3332 * @rmtoll IER RXPIE LL_I2S_EnableIT_RXP
3333 * @param SPIx SPI Instance
3334 * @retval None
3335 */
LL_I2S_EnableIT_RXP(SPI_TypeDef * SPIx)3336 __STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
3337 {
3338 LL_SPI_EnableIT_RXP(SPIx);
3339 }
3340
3341 /**
3342 * @brief Enable Tx Packet space available IT
3343 * @rmtoll IER TXPIE LL_I2S_EnableIT_TXP
3344 * @param SPIx SPI Instance
3345 * @retval None
3346 */
LL_I2S_EnableIT_TXP(SPI_TypeDef * SPIx)3347 __STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
3348 {
3349 LL_SPI_EnableIT_TXP(SPIx);
3350 }
3351
3352 /**
3353 * @brief Enable Underrun IT
3354 * @rmtoll IER UDRIE LL_I2S_EnableIT_UDR
3355 * @param SPIx SPI Instance
3356 * @retval None
3357 */
LL_I2S_EnableIT_UDR(SPI_TypeDef * SPIx)3358 __STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
3359 {
3360 LL_SPI_EnableIT_UDR(SPIx);
3361 }
3362
3363 /**
3364 * @brief Enable Overrun IT
3365 * @rmtoll IER OVRIE LL_I2S_EnableIT_OVR
3366 * @param SPIx SPI Instance
3367 * @retval None
3368 */
LL_I2S_EnableIT_OVR(SPI_TypeDef * SPIx)3369 __STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
3370 {
3371 LL_SPI_EnableIT_OVR(SPIx);
3372 }
3373
3374 /**
3375 * @brief Enable TI Frame Format Error IT
3376 * @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE
3377 * @param SPIx SPI Instance
3378 * @retval None
3379 */
LL_I2S_EnableIT_FRE(SPI_TypeDef * SPIx)3380 __STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
3381 {
3382 LL_SPI_EnableIT_FRE(SPIx);
3383 }
3384
3385 /**
3386 * @brief Disable Rx Packet available IT
3387 * @rmtoll IER RXPIE LL_I2S_DisableIT_RXP
3388 * @param SPIx SPI Instance
3389 * @retval None
3390 */
LL_I2S_DisableIT_RXP(SPI_TypeDef * SPIx)3391 __STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
3392 {
3393 LL_SPI_DisableIT_RXP(SPIx);
3394 }
3395
3396 /**
3397 * @brief Disable Tx Packet space available IT
3398 * @rmtoll IER TXPIE LL_I2S_DisableIT_TXP
3399 * @param SPIx SPI Instance
3400 * @retval None
3401 */
LL_I2S_DisableIT_TXP(SPI_TypeDef * SPIx)3402 __STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
3403 {
3404 LL_SPI_DisableIT_TXP(SPIx);
3405 }
3406
3407 /**
3408 * @brief Disable Underrun IT
3409 * @rmtoll IER UDRIE LL_I2S_DisableIT_UDR
3410 * @param SPIx SPI Instance
3411 * @retval None
3412 */
LL_I2S_DisableIT_UDR(SPI_TypeDef * SPIx)3413 __STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
3414 {
3415 LL_SPI_DisableIT_UDR(SPIx);
3416 }
3417
3418 /**
3419 * @brief Disable Overrun IT
3420 * @rmtoll IER OVRIE LL_I2S_DisableIT_OVR
3421 * @param SPIx SPI Instance
3422 * @retval None
3423 */
LL_I2S_DisableIT_OVR(SPI_TypeDef * SPIx)3424 __STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
3425 {
3426 LL_SPI_DisableIT_OVR(SPIx);
3427 }
3428
3429 /**
3430 * @brief Disable TI Frame Format Error IT
3431 * @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE
3432 * @param SPIx SPI Instance
3433 * @retval None
3434 */
LL_I2S_DisableIT_FRE(SPI_TypeDef * SPIx)3435 __STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
3436 {
3437 LL_SPI_DisableIT_FRE(SPIx);
3438 }
3439
3440 /**
3441 * @brief Check if Rx Packet available IT is enabled
3442 * @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP
3443 * @param SPIx SPI Instance
3444 * @retval State of bit (1 or 0)
3445 */
LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef * SPIx)3446 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
3447 {
3448 return LL_SPI_IsEnabledIT_RXP(SPIx);
3449 }
3450
3451 /**
3452 * @brief Check if Tx Packet space available IT is enabled
3453 * @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP
3454 * @param SPIx SPI Instance
3455 * @retval State of bit (1 or 0)
3456 */
LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef * SPIx)3457 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
3458 {
3459 return LL_SPI_IsEnabledIT_TXP(SPIx);
3460 }
3461
3462 /**
3463 * @brief Check if Underrun IT is enabled
3464 * @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR
3465 * @param SPIx SPI Instance
3466 * @retval State of bit (1 or 0)
3467 */
LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef * SPIx)3468 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
3469 {
3470 return LL_SPI_IsEnabledIT_UDR(SPIx);
3471 }
3472
3473 /**
3474 * @brief Check if Overrun IT is enabled
3475 * @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR
3476 * @param SPIx SPI Instance
3477 * @retval State of bit (1 or 0)
3478 */
LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef * SPIx)3479 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
3480 {
3481 return LL_SPI_IsEnabledIT_OVR(SPIx);
3482 }
3483
3484 /**
3485 * @brief Check if TI Frame Format Error IT is enabled
3486 * @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE
3487 * @param SPIx SPI Instance
3488 * @retval State of bit (1 or 0)
3489 */
LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef * SPIx)3490 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
3491 {
3492 return LL_SPI_IsEnabledIT_FRE(SPIx);
3493 }
3494
3495 /**
3496 * @}
3497 */
3498
3499 /** @defgroup I2S_LL_EF_DMA_Management DMA_Management
3500 * @{
3501 */
3502
3503 /**
3504 * @brief Enable DMA Rx
3505 * @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX
3506 * @param SPIx SPI Instance
3507 * @retval None
3508 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)3509 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
3510 {
3511 LL_SPI_EnableDMAReq_RX(SPIx);
3512 }
3513
3514 /**
3515 * @brief Disable DMA Rx
3516 * @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX
3517 * @param SPIx SPI Instance
3518 * @retval None
3519 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)3520 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
3521 {
3522 LL_SPI_DisableDMAReq_RX(SPIx);
3523 }
3524
3525 /**
3526 * @brief Check if DMA Rx is enabled
3527 * @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
3528 * @param SPIx SPI Instance
3529 * @retval State of bit (1 or 0)
3530 */
LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)3531 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
3532 {
3533 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
3534 }
3535
3536 /**
3537 * @brief Enable DMA Tx
3538 * @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX
3539 * @param SPIx SPI Instance
3540 * @retval None
3541 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)3542 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
3543 {
3544 LL_SPI_EnableDMAReq_TX(SPIx);
3545 }
3546
3547 /**
3548 * @brief Disable DMA Tx
3549 * @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX
3550 * @param SPIx SPI Instance
3551 * @retval None
3552 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)3553 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
3554 {
3555 LL_SPI_DisableDMAReq_TX(SPIx);
3556 }
3557
3558 /**
3559 * @brief Check if DMA Tx is enabled
3560 * @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
3561 * @param SPIx SPI Instance
3562 * @retval State of bit (1 or 0)
3563 */
LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)3564 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
3565 {
3566 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
3567 }
3568
3569 /**
3570 * @}
3571 */
3572
3573 /** @defgroup I2S_LL_EF_DATA_Management DATA_Management
3574 * @{
3575 */
3576
3577 /**
3578 * @brief Read Data Register
3579 * @rmtoll RXDR . LL_I2S_ReceiveData16
3580 * @param SPIx SPI Instance
3581 * @retval 0..0xFFFF
3582 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)3583 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
3584 {
3585 return LL_SPI_ReceiveData16(SPIx);
3586 }
3587
3588 /**
3589 * @brief Read Data Register
3590 * @rmtoll RXDR . LL_I2S_ReceiveData32
3591 * @param SPIx SPI Instance
3592 * @retval 0..0xFFFFFFFF
3593 */
LL_I2S_ReceiveData32(SPI_TypeDef * SPIx)3594 __STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
3595 {
3596 return LL_SPI_ReceiveData32(SPIx);
3597 }
3598
3599 /**
3600 * @brief Write Data Register
3601 * @rmtoll TXDR . LL_I2S_TransmitData16
3602 * @param SPIx SPI Instance
3603 * @param TxData 0..0xFFFF
3604 * @retval None
3605 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)3606 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
3607 {
3608 LL_SPI_TransmitData16(SPIx, TxData);
3609 }
3610
3611 /**
3612 * @brief Write Data Register
3613 * @rmtoll TXDR . LL_I2S_TransmitData32
3614 * @param SPIx SPI Instance
3615 * @param TxData 0..0xFFFFFFFF
3616 * @retval None
3617 */
LL_I2S_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)3618 __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
3619 {
3620 LL_SPI_TransmitData32(SPIx, TxData);
3621 }
3622
3623
3624 /**
3625 * @}
3626 */
3627
3628
3629 #if defined(USE_FULL_LL_DRIVER)
3630 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
3631 * @{
3632 */
3633
3634 ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
3635 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct);
3636 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
3637 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
3638
3639 /**
3640 * @}
3641 */
3642 #endif /* USE_FULL_LL_DRIVER */
3643
3644 /**
3645 * @}
3646 */
3647
3648 /**
3649 * @}
3650 */
3651
3652 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
3653
3654 /**
3655 * @}
3656 */
3657
3658 #ifdef __cplusplus
3659 }
3660 #endif
3661
3662 #endif /* STM32H5xx_LL_SPI_H */
3663
