1059   MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);  in LL_SPI_SetUDRConfiguration()
1073   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));  in LL_SPI_GetUDRConfiguration()
1089   MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);  in LL_SPI_SetUDRDetection()
1103   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));  in LL_SPI_GetUDRDetection()
1240   MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);  in LL_SPI_SetBaudRatePrescaler()
1259   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));  in LL_SPI_GetBaudRatePrescaler()
1399   MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);  in LL_SPI_SetDataWidth()
1439   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));  in LL_SPI_GetDataWidth()
1468   MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);  in LL_SPI_SetFIFOThreshold()
1495   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));  in LL_SPI_GetFIFOThreshold()
1507   SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);  in LL_SPI_EnableCRC()
1518   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);  in LL_SPI_DisableCRC()
1529   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);  in LL_SPI_IsEnabledCRC()
1571   MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);  in LL_SPI_SetCRCWidth()
1611   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));  in LL_SPI_GetCRCWidth()
2358   SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);  in LL_SPI_EnableDMAReq_RX()
2369   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);  in LL_SPI_DisableDMAReq_RX()
2380   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);  in LL_SPI_IsEnabledDMAReq_RX()
2391   SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);  in LL_SPI_EnableDMAReq_TX()
2402   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);  in LL_SPI_DisableDMAReq_TX()
2413   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);  in LL_SPI_IsEnabledDMAReq_TX()