Lines Matching refs:CFG1

1108   MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);  in LL_SPI_SetUDRConfiguration()
1121 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); in LL_SPI_GetUDRConfiguration()
1261 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); in LL_SPI_SetBaudRatePrescaler()
1282 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); in LL_SPI_GetBaudRatePrescaler()
1422 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); in LL_SPI_SetDataWidth()
1462 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); in LL_SPI_GetDataWidth()
1491 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); in LL_SPI_SetFIFOThreshold()
1518 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); in LL_SPI_GetFIFOThreshold()
1530 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_EnableCRC()
1541 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); in LL_SPI_DisableCRC()
1552 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); in LL_SPI_IsEnabledCRC()
1594 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength); in LL_SPI_SetCRCWidth()
1634 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE)); in LL_SPI_GetCRCWidth()
2326 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); in LL_SPI_EnableDMAReq_RX()
2337 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); in LL_SPI_DisableDMAReq_RX()
2348 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); in LL_SPI_IsEnabledDMAReq_RX()
2359 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); in LL_SPI_EnableDMAReq_TX()
2370 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); in LL_SPI_DisableDMAReq_TX()
2381 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); in LL_SPI_IsEnabledDMAReq_TX()