1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_SPI_H
21 #define STM32U5xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI2) || defined(SPI3)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private variables ---------------------------------------------------------*/
41
42 /* Private constants ---------------------------------------------------------*/
43 /** Legacy definitions for compatibility purpose
44 @cond 0
45 */
46 #define LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED LL_SPI_UDR_CONFIG_LAST_RECEIVED
47 /**
48 @endcond
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
53 * @{
54 */
55 #if defined(IS_SPI_GRP2_INSTANCE)
56 #define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__)
57 #define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) IS_SPI_GRP2_INSTANCE(__INSTANCE__)
58 #else
59 #define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__)
60 #endif /* SPI_TRIG_GRP2 */
61 /**
62 * @}
63 */
64
65 /* Exported types ------------------------------------------------------------*/
66 #if defined(USE_FULL_LL_DRIVER)
67 /** @defgroup SPI_LL_Exported_Types SPI Exported Types
68 * @{
69 */
70
71 /**
72 * @brief SPI Init structures definition
73 */
74 typedef struct
75 {
76 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
77 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
78
79 This feature can be modified afterwards using unitary function
80 @ref LL_SPI_SetTransferDirection().*/
81
82 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
83 This parameter can be a value of @ref SPI_LL_EC_MODE.
84
85 This feature can be modified afterwards using unitary function
86 @ref LL_SPI_SetMode().*/
87
88 uint32_t DataWidth; /*!< Specifies the SPI data width.
89 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
90
91 This feature can be modified afterwards using unitary function
92 @ref LL_SPI_SetDataWidth().*/
93
94 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
95 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
96
97 This feature can be modified afterwards using unitary function
98 @ref LL_SPI_SetClockPolarity().*/
99
100 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
101 This parameter can be a value of @ref SPI_LL_EC_PHASE.
102
103 This feature can be modified afterwards using unitary function
104 @ref LL_SPI_SetClockPhase().*/
105
106 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
107 or by software using the SSI bit.
108
109 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
110
111 This feature can be modified afterwards using unitary function
112 @ref LL_SPI_SetNSSMode().*/
113
114 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
115 the transmit and receive SCK clock.
116 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
117 @note The communication clock is derived from the master clock.
118 The slave clock does not need to be set.
119
120 This feature can be modified afterwards using unitary function
121 @ref LL_SPI_SetBaudRatePrescaler().*/
122
123 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
124 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
125
126 This feature can be modified afterwards using unitary function
127 @ref LL_SPI_SetTransferBitOrder().*/
128
129 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
130 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
131
132 This feature can be modified afterwards using unitary functions
133 @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
134
135 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
136 This parameter must be a number between Min_Data = 0x00
137 and Max_Data = 0xFFFFFFFF.
138
139 This feature can be modified afterwards using unitary function
140 @ref LL_SPI_SetCRCPolynomial().*/
141
142 } LL_SPI_InitTypeDef;
143
144 /**
145 * @}
146 */
147 #endif /*USE_FULL_LL_DRIVER*/
148
149 /* Exported types ------------------------------------------------------------*/
150
151 /* Exported constants --------------------------------------------------------*/
152 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
153 * @{
154 */
155
156 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
157 * @brief Flags defines which can be used with LL_SPI_ReadReg function
158 * @{
159 */
160 #define LL_SPI_SR_RXP (SPI_SR_RXP)
161 #define LL_SPI_SR_TXP (SPI_SR_TXP)
162 #define LL_SPI_SR_DXP (SPI_SR_DXP)
163 #define LL_SPI_SR_EOT (SPI_SR_EOT)
164 #define LL_SPI_SR_TXTF (SPI_SR_TXTF)
165 #define LL_SPI_SR_UDR (SPI_SR_UDR)
166 #define LL_SPI_SR_CRCE (SPI_SR_CRCE)
167 #define LL_SPI_SR_MODF (SPI_SR_MODF)
168 #define LL_SPI_SR_OVR (SPI_SR_OVR)
169 #define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
170 #define LL_SPI_SR_SUSP (SPI_SR_SUSP)
171 #define LL_SPI_SR_TXC (SPI_SR_TXC)
172 #define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
173 /**
174 * @}
175 */
176
177 /** @defgroup SPI_LL_EC_IT IT Defines
178 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
179 * @{
180 */
181 #define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
182 #define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
183 #define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
184 #define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
185 #define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
186 #define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
187 #define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
188 #define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
189 #define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
190 #define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
191 /**
192 * @}
193 */
194
195 /** @defgroup SPI_LL_EC_MODE Mode
196 * @{
197 */
198 #define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
199 #define LL_SPI_MODE_SLAVE (0x00000000UL)
200 /**
201 * @}
202 */
203
204 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
205 * @{
206 */
207 #define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
208 #define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
209 /**
210 * @}
211 */
212
213 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
214 * @{
215 */
216 #define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
217 #define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
218 #define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
219 #define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
220 #define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
221 #define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
222 #define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
223 #define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
224 #define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
225 #define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
226 #define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
227 #define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
228 #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
229 #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
230 #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
231 #define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
232 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
233 /**
234 * @}
235 */
236
237 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
238 * @{
239 */
240 #define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
241 #define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
242 #define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
243 #define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
244 #define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
245 #define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
246 #define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
247 #define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
248 #define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
249 #define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
250 #define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
251 #define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
252 #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
253 #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
254 #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
255 #define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
256 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
257 /**
258 * @}
259 */
260
261 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
262 * @{
263 */
264 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
265 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
266 /**
267 * @}
268 */
269
270 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
271 * @{
272 */
273 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
274 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
275 /**
276 * @}
277 */
278
279 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
280 * @{
281 */
282 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
283 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG)
284 /**
285 * @}
286 */
287
288 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
289 * @{
290 */
291 #define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
292 #define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
293 /**
294 * @}
295 */
296
297 /** @defgroup SPI_LL_EC_PHASE Phase
298 * @{
299 */
300 #define LL_SPI_PHASE_1EDGE (0x00000000UL)
301 #define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
302 /**
303 * @}
304 */
305
306 /** @defgroup SPI_LL_EC_POLARITY Polarity
307 * @{
308 */
309 #define LL_SPI_POLARITY_LOW (0x00000000UL)
310 #define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
311 /**
312 * @}
313 */
314
315 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
316 * @{
317 */
318 #define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
319 #define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
320 /**
321 * @}
322 */
323
324 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
325 * @{
326 */
327 #define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS)
328 #define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
329 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
330 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
331 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
332 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
333 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
334 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
335 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
336 /**
337 * @}
338 */
339
340 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
341 * @{
342 */
343 #define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
344 #define LL_SPI_MSB_FIRST (0x00000000UL)
345 /**
346 * @}
347 */
348
349 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
350 * @{
351 */
352 #define LL_SPI_FULL_DUPLEX (0x00000000UL)
353 #define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
354 #define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
355 #define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
356 #define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
357 /**
358 * @}
359 */
360
361 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
362 * @{
363 */
364 #define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
365 #define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
366 #define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
367 #define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
368 #define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
369 #define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
370 #define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
371 #define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
372 #define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
373 #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
374 #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
375 #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
376 #define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
377 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
378 #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
379 #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
380 #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
381 #define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
382 #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
383 #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
384 #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
385 #define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
386 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
387 #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
388 #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
389 #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
390 #define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
391 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
392 #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
393 #define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
394 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
395 #define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
396 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
397 #define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
398 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
399 /**
400 * @}
401 */
402
403 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
404 * @{
405 */
406 #define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
407 #define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
408 #define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
409 #define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
410 #define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
411 #define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
412 #define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
413 #define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
414 #define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
415 #define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
416 #define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
417 #define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
418 #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
419 #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
420 #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
421 #define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
422 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
423 /**
424 * @}
425 */
426
427 #if defined(USE_FULL_LL_DRIVER)
428
429 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
430 * @{
431 */
432 #define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
433 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
434 /**
435 * @}
436 */
437 #endif /* USE_FULL_LL_DRIVER */
438
439 /** @defgroup SPI_LL_EC_CRC CRC
440 * @{
441 */
442 #define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
443 #define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
444 #define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
445 #define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
446 #define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
447 #define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
448 #define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
449 #define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
450 #define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
451 #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
452 #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
453 #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
454 #define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
455 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
456 #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
457 #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
458 #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
459 #define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
460 #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
461 #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
462 #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
463 #define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
464 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
465 #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
466 #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
467 #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
468 #define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
469 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
470 #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
471 #define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
472 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
473 #define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
474 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
475 #define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
476 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
477 /**
478 * @}
479 */
480
481 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
482 * @{
483 */
484 #define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
485 #define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
486 #define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
487 /**
488 * @}
489 */
490
491 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
492 * @{
493 */
494 #define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
495 #define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
496 #define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
497 #define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
498 /**
499 * @}
500 */
501
502 /** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
503 * @brief SPI Autonomous Trigger selection
504 * @{
505 */
506 #define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 and SPI2 */
507 #if defined(SPI3)
508 #define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */
509 #endif /* SPI3 */
510
511 /*!< HW Trigger signal is GPDMA_CH0_TRG */
512 #define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U))
513 /*!< HW Trigger signal is GPDMA_CH1_TRG */
514 #define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
515 /*!< HW Trigger signal is GPDMA_CH2_TRG */
516 #define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
517 /*!< HW Trigger signal is GPDMA_CH3_TRG */
518 #define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
519 /*!< HW Trigger signal is EXTI4_TRG */
520 #define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
521 /*!< HW Trigger signal is EXTI9_TRG */
522 #define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
523 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
524 #define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
525 /*!< HW Trigger signal is LPTIM2_CH1_TRG */
526 #define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
527 /*!< HW Trigger signal is COMP1_TRG */
528 #define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
529 /*!< HW Trigger signal is COMP2_TRG */
530 #define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
531 /*!< HW Trigger signal is RTC_ALRA_TRG */
532 #define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
533 /*!< HW Trigger signal is RTC_WUT_TRG */
534 #define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
535
536 #if defined(LL_SPI_TRIG_GRP2)
537 /*!< HW Trigger signal is LPDMA_CH0_TRG */
538 #define LL_SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U))
539 /*!< HW Trigger signal is LPDMA_CH1_TRG */
540 #define LL_SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
541 /*!< HW Trigger signal is LPDMA_CH2_TRG */
542 #define LL_SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
543 /*!< HW Trigger signal is LPDMA_CH3_TRG */
544 #define LL_SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
545 /*!< HW Trigger signal is EXTI4_TRG */
546 #define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
547 /*!< HW Trigger signal is EXTI8_TRG */
548 #define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
549 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
550 #define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
551 /*!< HW Trigger signal is LPTIM3_CH1_TRG */
552 #define LL_SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
553 /*!< HW Trigger signal is COMP1_TRG */
554 #define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
555 /*!< HW Trigger signal is COMP2_TRG */
556 #define LL_SPI_GRP2_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
557 /*!< HW Trigger signal is RTC_ALRA_TRG */
558 #define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
559 /*!< HW Trigger signal is RTC_WUT_TRG */
560 #define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
561 #endif /* LL_SPI_TRIG_GRP2 */
562 /**
563 * @}
564 */
565
566 /** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
567 * @brief SPI Autonomous Trigger Polarity
568 * @{
569 */
570 #define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */
571 #define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */
572 /**
573 * @}
574 */
575
576 /**
577 * @}
578 */
579
580 /* Exported macro ------------------------------------------------------------*/
581 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
582 * @{
583 */
584
585 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
586 * @{
587 */
588
589 /**
590 * @brief Write a value in SPI register
591 * @param __INSTANCE__ SPI Instance
592 * @param __REG__ Register to be written
593 * @param __VALUE__ Value to be written in the register
594 * @retval None
595 */
596 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
597
598 /**
599 * @brief Read a value in SPI register
600 * @param __INSTANCE__ SPI Instance
601 * @param __REG__ Register to be read
602 * @retval Register value
603 */
604 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
605 /**
606 * @}
607 */
608
609 /**
610 * @}
611 */
612
613
614 /* Exported functions --------------------------------------------------------*/
615
616 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
617 * @{
618 */
619
620 /** @defgroup SPI_LL_EF_Configuration Configuration
621 * @{
622 */
623
624 /**
625 * @brief Enable SPI peripheral
626 * @rmtoll CR1 SPE LL_SPI_Enable
627 * @param SPIx SPI Instance
628 * @retval None
629 */
LL_SPI_Enable(SPI_TypeDef * SPIx)630 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
631 {
632 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
633 }
634
635 /**
636 * @brief Disable SPI peripheral
637 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
638 * @rmtoll CR1 SPE LL_SPI_Disable
639 * @param SPIx SPI Instance
640 * @retval None
641 */
LL_SPI_Disable(SPI_TypeDef * SPIx)642 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
643 {
644 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
645 }
646
647 /**
648 * @brief Check if SPI peripheral is enabled
649 * @rmtoll CR1 SPE LL_SPI_IsEnabled
650 * @param SPIx SPI Instance
651 * @retval State of bit (1 or 0)
652 */
LL_SPI_IsEnabled(const SPI_TypeDef * SPIx)653 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
654 {
655 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
656 }
657
658 /**
659 * @brief Swap the MOSI and MISO pin
660 * @note This configuration can not be changed when SPI is enabled.
661 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
662 * @param SPIx SPI Instance
663 * @retval None
664 */
LL_SPI_EnableIOSwap(SPI_TypeDef * SPIx)665 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
666 {
667 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
668 }
669
670 /**
671 * @brief Restore default function for MOSI and MISO pin
672 * @note This configuration can not be changed when SPI is enabled.
673 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
674 * @param SPIx SPI Instance
675 * @retval None
676 */
LL_SPI_DisableIOSwap(SPI_TypeDef * SPIx)677 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
678 {
679 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
680 }
681
682 /**
683 * @brief Check if MOSI and MISO pin are swapped
684 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
685 * @param SPIx SPI Instance
686 * @retval State of bit (1 or 0)
687 */
LL_SPI_IsEnabledIOSwap(const SPI_TypeDef * SPIx)688 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
689 {
690 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
691 }
692
693 /**
694 * @brief Enable GPIO control
695 * @note This configuration can not be changed when SPI is enabled.
696 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
697 * @param SPIx SPI Instance
698 * @retval None
699 */
LL_SPI_EnableGPIOControl(SPI_TypeDef * SPIx)700 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
701 {
702 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
703 }
704
705 /**
706 * @brief Disable GPIO control
707 * @note This configuration can not be changed when SPI is enabled.
708 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
709 * @param SPIx SPI Instance
710 * @retval None
711 */
LL_SPI_DisableGPIOControl(SPI_TypeDef * SPIx)712 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
713 {
714 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
715 }
716
717 /**
718 * @brief Check if GPIO control is active
719 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
720 * @param SPIx SPI Instance
721 * @retval State of bit (1 or 0)
722 */
LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef * SPIx)723 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
724 {
725 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
726 }
727
728 /**
729 * @brief Set SPI Mode to Master or Slave
730 * @note This configuration can not be changed when SPI is enabled.
731 * @rmtoll CFG2 MASTER LL_SPI_SetMode
732 * @param SPIx SPI Instance
733 * @param Mode This parameter can be one of the following values:
734 * @arg @ref LL_SPI_MODE_MASTER
735 * @arg @ref LL_SPI_MODE_SLAVE
736 * @retval None
737 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)738 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
739 {
740 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
741 }
742
743 /**
744 * @brief Get SPI Mode (Master or Slave)
745 * @rmtoll CFG2 MASTER LL_SPI_GetMode
746 * @param SPIx SPI Instance
747 * @retval Returned value can be one of the following values:
748 * @arg @ref LL_SPI_MODE_MASTER
749 * @arg @ref LL_SPI_MODE_SLAVE
750 */
LL_SPI_GetMode(const SPI_TypeDef * SPIx)751 __STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
752 {
753 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
754 }
755
756 /**
757 * @brief Configure the Idleness applied by master between active edge of SS and first send data
758 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
759 * @param SPIx SPI Instance
760 * @param MasterSSIdleness This parameter can be one of the following values:
761 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
762 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
763 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
764 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
765 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
766 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
767 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
768 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
769 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
770 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
771 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
772 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
773 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
774 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
775 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
776 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
777 * @retval None
778 */
LL_SPI_SetMasterSSIdleness(SPI_TypeDef * SPIx,uint32_t MasterSSIdleness)779 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
780 {
781 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
782 }
783
784 /**
785 * @brief Get the configured Idleness applied by master
786 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
787 * @param SPIx SPI Instance
788 * @retval Returned value can be one of the following values:
789 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
790 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
791 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
792 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
793 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
794 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
795 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
796 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
797 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
798 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
799 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
800 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
801 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
802 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
803 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
804 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
805 */
LL_SPI_GetMasterSSIdleness(const SPI_TypeDef * SPIx)806 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
807 {
808 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
809 }
810
811 /**
812 * @brief Configure the idleness applied by master between data frame
813 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
814 * @param SPIx SPI Instance
815 * @param MasterInterDataIdleness This parameter can be one of the following values:
816 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
817 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
818 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
819 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
820 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
821 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
822 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
823 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
824 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
825 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
826 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
827 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
828 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
829 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
830 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
831 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
832 * @retval None
833 */
LL_SPI_SetInterDataIdleness(SPI_TypeDef * SPIx,uint32_t MasterInterDataIdleness)834 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
835 {
836 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
837 }
838
839 /**
840 * @brief Get the configured inter data idleness
841 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
842 * @param SPIx SPI Instance
843 * @retval Returned value can be one of the following values:
844 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
845 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
846 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
847 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
848 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
849 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
850 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
851 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
852 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
853 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
854 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
855 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
856 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
857 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
858 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
859 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
860 */
LL_SPI_GetInterDataIdleness(const SPI_TypeDef * SPIx)861 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
862 {
863 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
864 }
865
866 /**
867 * @brief Set transfer size
868 * @note Count is the number of frame to be transferred
869 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
870 * @param SPIx SPI Instance
871 * @param Count 0..0xFFFF
872 * @retval None
873 */
LL_SPI_SetTransferSize(SPI_TypeDef * SPIx,uint32_t Count)874 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
875 {
876 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
877 }
878
879 /**
880 * @brief Get transfer size
881 * @note Count is the number of frame to be transferred
882 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
883 * @param SPIx SPI Instance
884 * @retval 0..0xFFFF
885 */
LL_SPI_GetTransferSize(const SPI_TypeDef * SPIx)886 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
887 {
888 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
889 }
890
891 /**
892 * @brief Lock the AF configuration of associated IOs
893 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
894 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
895 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
896 * @param SPIx SPI Instance
897 * @retval None
898 */
LL_SPI_EnableIOLock(SPI_TypeDef * SPIx)899 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
900 {
901 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
902 }
903
904 /**
905 * @brief Check if the AF configuration is locked.
906 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
907 * @param SPIx SPI Instance
908 * @retval State of bit (1 or 0)
909 */
LL_SPI_IsEnabledIOLock(const SPI_TypeDef * SPIx)910 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
911 {
912 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
913 }
914
915 /**
916 * @brief Set Tx CRC Initialization Pattern
917 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
918 * @param SPIx SPI Instance
919 * @param TXCRCInitAll This parameter can be one of the following values:
920 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
921 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
922 * @retval None
923 */
LL_SPI_SetTxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t TXCRCInitAll)924 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
925 {
926 MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll);
927 }
928
929 /**
930 * @brief Get Tx CRC Initialization Pattern
931 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
932 * @param SPIx SPI Instance
933 * @retval Returned value can be one of the following values:
934 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
935 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
936 */
LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef * SPIx)937 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
938 {
939 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
940 }
941
942 /**
943 * @brief Set Rx CRC Initialization Pattern
944 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
945 * @param SPIx SPI Instance
946 * @param RXCRCInitAll This parameter can be one of the following values:
947 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
948 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
949 * @retval None
950 */
LL_SPI_SetRxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t RXCRCInitAll)951 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
952 {
953 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
954 }
955
956 /**
957 * @brief Get Rx CRC Initialization Pattern
958 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
959 * @param SPIx SPI Instance
960 * @retval Returned value can be one of the following values:
961 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
962 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
963 */
LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef * SPIx)964 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
965 {
966 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
967 }
968
969 /**
970 * @brief Set internal SS input level ignoring what comes from PIN.
971 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
972 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
973 * @param SPIx SPI Instance
974 * @param SSLevel This parameter can be one of the following values:
975 * @arg @ref LL_SPI_SS_LEVEL_HIGH
976 * @arg @ref LL_SPI_SS_LEVEL_LOW
977 * @retval None
978 */
LL_SPI_SetInternalSSLevel(SPI_TypeDef * SPIx,uint32_t SSLevel)979 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
980 {
981 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
982 }
983
984 /**
985 * @brief Get internal SS input level
986 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
987 * @param SPIx SPI Instance
988 * @retval Returned value can be one of the following values:
989 * @arg @ref LL_SPI_SS_LEVEL_HIGH
990 * @arg @ref LL_SPI_SS_LEVEL_LOW
991 */
LL_SPI_GetInternalSSLevel(const SPI_TypeDef * SPIx)992 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
993 {
994 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
995 }
996
997 /**
998 * @brief Enable CRC computation on 33/17 bits
999 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
1000 * @param SPIx SPI Instance
1001 * @retval None
1002 */
LL_SPI_EnableFullSizeCRC(SPI_TypeDef * SPIx)1003 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
1004 {
1005 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
1006 }
1007
1008 /**
1009 * @brief Disable CRC computation on 33/17 bits
1010 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
1011 * @param SPIx SPI Instance
1012 * @retval None
1013 */
LL_SPI_DisableFullSizeCRC(SPI_TypeDef * SPIx)1014 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
1015 {
1016 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
1017 }
1018
1019 /**
1020 * @brief Check if Enable CRC computation on 33/17 bits is enabled
1021 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
1022 * @param SPIx SPI Instance
1023 * @retval State of bit (1 or 0)
1024 */
LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef * SPIx)1025 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
1026 {
1027 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
1028 }
1029
1030 /**
1031 * @brief Suspend an ongoing transfer for Master configuration
1032 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
1033 * @param SPIx SPI Instance
1034 * @retval None
1035 */
LL_SPI_SuspendMasterTransfer(SPI_TypeDef * SPIx)1036 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
1037 {
1038 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
1039 }
1040
1041 /**
1042 * @brief Start effective transfer on wire for Master configuration
1043 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
1044 * @param SPIx SPI Instance
1045 * @retval None
1046 */
LL_SPI_StartMasterTransfer(SPI_TypeDef * SPIx)1047 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
1048 {
1049 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
1050 }
1051
1052 /**
1053 * @brief Check if there is an unfinished master transfer
1054 * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
1055 * @param SPIx SPI Instance
1056 * @retval State of bit (1 or 0)
1057 */
LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef * SPIx)1058 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
1059 {
1060 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
1061 }
1062
1063 /**
1064 * @brief Enable Master Rx auto suspend in case of overrun
1065 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
1066 * @param SPIx SPI Instance
1067 * @retval None
1068 */
LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1069 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1070 {
1071 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
1072 }
1073
1074 /**
1075 * @brief Disable Master Rx auto suspend in case of overrun
1076 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
1077 * @param SPIx SPI Instance
1078 * @retval None
1079 */
LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1080 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1081 {
1082 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
1083 }
1084
1085 /**
1086 * @brief Check if Master Rx auto suspend is activated
1087 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1088 * @param SPIx SPI Instance
1089 * @retval State of bit (1 or 0)
1090 */
LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef * SPIx)1091 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
1092 {
1093 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1094 }
1095
1096 /**
1097 * @brief Set Underrun behavior
1098 * @note This configuration can not be changed when SPI is enabled.
1099 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1100 * @param SPIx SPI Instance
1101 * @param UDRConfig This parameter can be one of the following values:
1102 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1103 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1104 * @retval None
1105 */
LL_SPI_SetUDRConfiguration(SPI_TypeDef * SPIx,uint32_t UDRConfig)1106 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1107 {
1108 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1109 }
1110
1111 /**
1112 * @brief Get Underrun behavior
1113 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1114 * @param SPIx SPI Instance
1115 * @retval Returned value can be one of the following values:
1116 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1117 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1118 */
LL_SPI_GetUDRConfiguration(const SPI_TypeDef * SPIx)1119 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
1120 {
1121 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1122 }
1123
1124
1125 /**
1126 * @brief Set Serial protocol used
1127 * @note This configuration can not be changed when SPI is enabled.
1128 * @rmtoll CFG2 SP LL_SPI_SetStandard
1129 * @param SPIx SPI Instance
1130 * @param Standard This parameter can be one of the following values:
1131 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1132 * @arg @ref LL_SPI_PROTOCOL_TI
1133 * @retval None
1134 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1135 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1136 {
1137 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1138 }
1139
1140 /**
1141 * @brief Get Serial protocol used
1142 * @rmtoll CFG2 SP LL_SPI_GetStandard
1143 * @param SPIx SPI Instance
1144 * @retval Returned value can be one of the following values:
1145 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1146 * @arg @ref LL_SPI_PROTOCOL_TI
1147 */
LL_SPI_GetStandard(const SPI_TypeDef * SPIx)1148 __STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
1149 {
1150 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1151 }
1152
1153 /**
1154 * @brief Set Clock phase
1155 * @note This configuration can not be changed when SPI is enabled.
1156 * This bit is not used in SPI TI mode.
1157 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1158 * @param SPIx SPI Instance
1159 * @param ClockPhase This parameter can be one of the following values:
1160 * @arg @ref LL_SPI_PHASE_1EDGE
1161 * @arg @ref LL_SPI_PHASE_2EDGE
1162 * @retval None
1163 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)1164 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1165 {
1166 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1167 }
1168
1169 /**
1170 * @brief Get Clock phase
1171 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1172 * @param SPIx SPI Instance
1173 * @retval Returned value can be one of the following values:
1174 * @arg @ref LL_SPI_PHASE_1EDGE
1175 * @arg @ref LL_SPI_PHASE_2EDGE
1176 */
LL_SPI_GetClockPhase(const SPI_TypeDef * SPIx)1177 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
1178 {
1179 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1180 }
1181
1182 /**
1183 * @brief Set Clock polarity
1184 * @note This configuration can not be changed when SPI is enabled.
1185 * This bit is not used in SPI TI mode.
1186 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1187 * @param SPIx SPI Instance
1188 * @param ClockPolarity This parameter can be one of the following values:
1189 * @arg @ref LL_SPI_POLARITY_LOW
1190 * @arg @ref LL_SPI_POLARITY_HIGH
1191 * @retval None
1192 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1193 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1194 {
1195 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1196 }
1197
1198 /**
1199 * @brief Get Clock polarity
1200 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1201 * @param SPIx SPI Instance
1202 * @retval Returned value can be one of the following values:
1203 * @arg @ref LL_SPI_POLARITY_LOW
1204 * @arg @ref LL_SPI_POLARITY_HIGH
1205 */
LL_SPI_GetClockPolarity(const SPI_TypeDef * SPIx)1206 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
1207 {
1208 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1209 }
1210
1211 /**
1212 * @brief Set NSS polarity
1213 * @note This configuration can not be changed when SPI is enabled.
1214 * This bit is not used in SPI TI mode.
1215 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1216 * @param SPIx SPI Instance
1217 * @param NSSPolarity This parameter can be one of the following values:
1218 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1219 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1220 * @retval None
1221 */
LL_SPI_SetNSSPolarity(SPI_TypeDef * SPIx,uint32_t NSSPolarity)1222 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1223 {
1224 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1225 }
1226
1227 /**
1228 * @brief Get NSS polarity
1229 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1230 * @param SPIx SPI Instance
1231 * @retval Returned value can be one of the following values:
1232 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1233 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1234 */
LL_SPI_GetNSSPolarity(const SPI_TypeDef * SPIx)1235 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
1236 {
1237 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1238 }
1239
1240 /**
1241 * @brief Set Baudrate Prescaler
1242 * @note This configuration can not be changed when SPI is enabled.
1243 * SPI BaudRate = fPCLK/Pescaler.
1244 * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n
1245 * CFG1 BPASS LL_SPI_SetBaudRatePrescaler
1246 * @param SPIx SPI Instance
1247 * @param Baudrate This parameter can be one of the following values:
1248 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1249 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1250 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1251 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1252 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1253 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1254 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1255 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1256 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1257 * @retval None
1258 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t Baudrate)1259 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1260 {
1261 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
1262 }
1263
1264 /**
1265 * @brief Get Baudrate Prescaler
1266 * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n
1267 * CFG1 BPASS LL_SPI_GetBaudRatePrescaler
1268 * @param SPIx SPI Instance
1269 * @retval Returned value can be one of the following values:
1270 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1271 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1272 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1273 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1274 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1275 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1276 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1277 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1278 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1279 */
LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef * SPIx)1280 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
1281 {
1282 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
1283 }
1284
1285 /**
1286 * @brief Set Transfer Bit Order
1287 * @note This configuration can not be changed when SPI is enabled.
1288 * This bit is not used in SPI TI mode.
1289 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1290 * @param SPIx SPI Instance
1291 * @param BitOrder This parameter can be one of the following values:
1292 * @arg @ref LL_SPI_LSB_FIRST
1293 * @arg @ref LL_SPI_MSB_FIRST
1294 * @retval None
1295 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)1296 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1297 {
1298 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1299 }
1300
1301 /**
1302 * @brief Get Transfer Bit Order
1303 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1304 * @param SPIx SPI Instance
1305 * @retval Returned value can be one of the following values:
1306 * @arg @ref LL_SPI_LSB_FIRST
1307 * @arg @ref LL_SPI_MSB_FIRST
1308 */
LL_SPI_GetTransferBitOrder(const SPI_TypeDef * SPIx)1309 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
1310 {
1311 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1312 }
1313
1314 /**
1315 * @brief Set Transfer Mode
1316 * @note This configuration can not be changed when SPI is enabled except for half duplex direction
1317 * using LL_SPI_SetHalfDuplexDirection.
1318 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1319 * CFG2 COMM LL_SPI_SetTransferDirection
1320 * @param SPIx SPI Instance
1321 * @param TransferDirection This parameter can be one of the following values:
1322 * @arg @ref LL_SPI_FULL_DUPLEX
1323 * @arg @ref LL_SPI_SIMPLEX_TX
1324 * @arg @ref LL_SPI_SIMPLEX_RX
1325 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1326 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1327 * @retval None
1328 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)1329 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1330 {
1331 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1332 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1333 }
1334
1335 /**
1336 * @brief Get Transfer Mode
1337 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1338 * CFG2 COMM LL_SPI_GetTransferDirection
1339 * @param SPIx SPI Instance
1340 * @retval Returned value can be one of the following values:
1341 * @arg @ref LL_SPI_FULL_DUPLEX
1342 * @arg @ref LL_SPI_SIMPLEX_TX
1343 * @arg @ref LL_SPI_SIMPLEX_RX
1344 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1345 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1346 */
LL_SPI_GetTransferDirection(const SPI_TypeDef * SPIx)1347 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
1348 {
1349 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1350 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1351 return (Hddir | Comm);
1352 }
1353
1354 /**
1355 * @brief Set direction for Half-Duplex Mode
1356 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1357 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1358 * @param SPIx SPI Instance
1359 * @param HalfDuplexDirection This parameter can be one of the following values:
1360 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1361 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1362 * @retval None
1363 */
LL_SPI_SetHalfDuplexDirection(SPI_TypeDef * SPIx,uint32_t HalfDuplexDirection)1364 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1365 {
1366 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1367 }
1368
1369 /**
1370 * @brief Get direction for Half-Duplex Mode
1371 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1372 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1373 * @param SPIx SPI Instance
1374 * @retval Returned value can be one of the following values:
1375 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1376 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1377 */
LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef * SPIx)1378 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
1379 {
1380 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1381 }
1382
1383 /**
1384 * @brief Set Frame Data Size
1385 * @note This configuration can not be changed when SPI is enabled.
1386 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1387 * @param SPIx SPI Instance
1388 * @param DataWidth This parameter can be one of the following values:
1389 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1390 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1391 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1392 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1393 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1394 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1395 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1396 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1397 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1398 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1399 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1400 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1401 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1402 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1403 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1404 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1405 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1406 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1407 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1408 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1409 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1410 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1411 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1412 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1413 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1414 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1415 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1416 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1417 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1418 * @retval None
1419 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)1420 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1421 {
1422 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1423 }
1424
1425 /**
1426 * @brief Get Frame Data Size
1427 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1428 * @param SPIx SPI Instance
1429 * @retval Returned value can be one of the following values:
1430 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1431 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1432 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1433 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1434 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1435 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1436 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1437 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1438 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1439 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1440 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1441 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1442 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1443 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1444 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1445 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1446 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1447 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1448 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1449 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1450 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1451 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1452 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1453 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1454 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1455 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1456 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1457 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1458 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1459 */
LL_SPI_GetDataWidth(const SPI_TypeDef * SPIx)1460 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
1461 {
1462 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1463 }
1464
1465 /**
1466 * @brief Set threshold of FIFO that triggers a transfer event
1467 * @note This configuration can not be changed when SPI is enabled.
1468 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1469 * @param SPIx SPI Instance
1470 * @param Threshold This parameter can be one of the following values:
1471 * @arg @ref LL_SPI_FIFO_TH_01DATA
1472 * @arg @ref LL_SPI_FIFO_TH_02DATA
1473 * @arg @ref LL_SPI_FIFO_TH_03DATA
1474 * @arg @ref LL_SPI_FIFO_TH_04DATA
1475 * @arg @ref LL_SPI_FIFO_TH_05DATA
1476 * @arg @ref LL_SPI_FIFO_TH_06DATA
1477 * @arg @ref LL_SPI_FIFO_TH_07DATA
1478 * @arg @ref LL_SPI_FIFO_TH_08DATA
1479 * @arg @ref LL_SPI_FIFO_TH_09DATA
1480 * @arg @ref LL_SPI_FIFO_TH_10DATA
1481 * @arg @ref LL_SPI_FIFO_TH_11DATA
1482 * @arg @ref LL_SPI_FIFO_TH_12DATA
1483 * @arg @ref LL_SPI_FIFO_TH_13DATA
1484 * @arg @ref LL_SPI_FIFO_TH_14DATA
1485 * @arg @ref LL_SPI_FIFO_TH_15DATA
1486 * @arg @ref LL_SPI_FIFO_TH_16DATA
1487 * @retval None
1488 */
LL_SPI_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)1489 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1490 {
1491 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1492 }
1493
1494 /**
1495 * @brief Get threshold of FIFO that triggers a transfer event
1496 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1497 * @param SPIx SPI Instance
1498 * @retval Returned value can be one of the following values:
1499 * @arg @ref LL_SPI_FIFO_TH_01DATA
1500 * @arg @ref LL_SPI_FIFO_TH_02DATA
1501 * @arg @ref LL_SPI_FIFO_TH_03DATA
1502 * @arg @ref LL_SPI_FIFO_TH_04DATA
1503 * @arg @ref LL_SPI_FIFO_TH_05DATA
1504 * @arg @ref LL_SPI_FIFO_TH_06DATA
1505 * @arg @ref LL_SPI_FIFO_TH_07DATA
1506 * @arg @ref LL_SPI_FIFO_TH_08DATA
1507 * @arg @ref LL_SPI_FIFO_TH_09DATA
1508 * @arg @ref LL_SPI_FIFO_TH_10DATA
1509 * @arg @ref LL_SPI_FIFO_TH_11DATA
1510 * @arg @ref LL_SPI_FIFO_TH_12DATA
1511 * @arg @ref LL_SPI_FIFO_TH_13DATA
1512 * @arg @ref LL_SPI_FIFO_TH_14DATA
1513 * @arg @ref LL_SPI_FIFO_TH_15DATA
1514 * @arg @ref LL_SPI_FIFO_TH_16DATA
1515 */
LL_SPI_GetFIFOThreshold(const SPI_TypeDef * SPIx)1516 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
1517 {
1518 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1519 }
1520
1521 /**
1522 * @brief Enable CRC
1523 * @note This configuration can not be changed when SPI is enabled.
1524 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1525 * @param SPIx SPI Instance
1526 * @retval None
1527 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)1528 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1529 {
1530 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1531 }
1532
1533 /**
1534 * @brief Disable CRC
1535 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1536 * @param SPIx SPI Instance
1537 * @retval None
1538 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)1539 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1540 {
1541 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1542 }
1543
1544 /**
1545 * @brief Check if CRC is enabled
1546 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1547 * @param SPIx SPI Instance
1548 * @retval State of bit (1 or 0).
1549 */
LL_SPI_IsEnabledCRC(const SPI_TypeDef * SPIx)1550 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
1551 {
1552 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1553 }
1554
1555 /**
1556 * @brief Set CRC Length
1557 * @note This configuration can not be changed when SPI is enabled.
1558 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1559 * @param SPIx SPI Instance
1560 * @param CRCLength This parameter can be one of the following values:
1561 * @arg @ref LL_SPI_CRC_4BIT
1562 * @arg @ref LL_SPI_CRC_5BIT
1563 * @arg @ref LL_SPI_CRC_6BIT
1564 * @arg @ref LL_SPI_CRC_7BIT
1565 * @arg @ref LL_SPI_CRC_8BIT
1566 * @arg @ref LL_SPI_CRC_9BIT
1567 * @arg @ref LL_SPI_CRC_10BIT
1568 * @arg @ref LL_SPI_CRC_11BIT
1569 * @arg @ref LL_SPI_CRC_12BIT
1570 * @arg @ref LL_SPI_CRC_13BIT
1571 * @arg @ref LL_SPI_CRC_14BIT
1572 * @arg @ref LL_SPI_CRC_15BIT
1573 * @arg @ref LL_SPI_CRC_16BIT
1574 * @arg @ref LL_SPI_CRC_17BIT
1575 * @arg @ref LL_SPI_CRC_18BIT
1576 * @arg @ref LL_SPI_CRC_19BIT
1577 * @arg @ref LL_SPI_CRC_20BIT
1578 * @arg @ref LL_SPI_CRC_21BIT
1579 * @arg @ref LL_SPI_CRC_22BIT
1580 * @arg @ref LL_SPI_CRC_23BIT
1581 * @arg @ref LL_SPI_CRC_24BIT
1582 * @arg @ref LL_SPI_CRC_25BIT
1583 * @arg @ref LL_SPI_CRC_26BIT
1584 * @arg @ref LL_SPI_CRC_27BIT
1585 * @arg @ref LL_SPI_CRC_28BIT
1586 * @arg @ref LL_SPI_CRC_29BIT
1587 * @arg @ref LL_SPI_CRC_30BIT
1588 * @arg @ref LL_SPI_CRC_31BIT
1589 * @arg @ref LL_SPI_CRC_32BIT
1590 * @retval None
1591 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)1592 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1593 {
1594 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1595 }
1596
1597 /**
1598 * @brief Get CRC Length
1599 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1600 * @param SPIx SPI Instance
1601 * @retval Returned value can be one of the following values:
1602 * @arg @ref LL_SPI_CRC_4BIT
1603 * @arg @ref LL_SPI_CRC_5BIT
1604 * @arg @ref LL_SPI_CRC_6BIT
1605 * @arg @ref LL_SPI_CRC_7BIT
1606 * @arg @ref LL_SPI_CRC_8BIT
1607 * @arg @ref LL_SPI_CRC_9BIT
1608 * @arg @ref LL_SPI_CRC_10BIT
1609 * @arg @ref LL_SPI_CRC_11BIT
1610 * @arg @ref LL_SPI_CRC_12BIT
1611 * @arg @ref LL_SPI_CRC_13BIT
1612 * @arg @ref LL_SPI_CRC_14BIT
1613 * @arg @ref LL_SPI_CRC_15BIT
1614 * @arg @ref LL_SPI_CRC_16BIT
1615 * @arg @ref LL_SPI_CRC_17BIT
1616 * @arg @ref LL_SPI_CRC_18BIT
1617 * @arg @ref LL_SPI_CRC_19BIT
1618 * @arg @ref LL_SPI_CRC_20BIT
1619 * @arg @ref LL_SPI_CRC_21BIT
1620 * @arg @ref LL_SPI_CRC_22BIT
1621 * @arg @ref LL_SPI_CRC_23BIT
1622 * @arg @ref LL_SPI_CRC_24BIT
1623 * @arg @ref LL_SPI_CRC_25BIT
1624 * @arg @ref LL_SPI_CRC_26BIT
1625 * @arg @ref LL_SPI_CRC_27BIT
1626 * @arg @ref LL_SPI_CRC_28BIT
1627 * @arg @ref LL_SPI_CRC_29BIT
1628 * @arg @ref LL_SPI_CRC_30BIT
1629 * @arg @ref LL_SPI_CRC_31BIT
1630 * @arg @ref LL_SPI_CRC_32BIT
1631 */
LL_SPI_GetCRCWidth(const SPI_TypeDef * SPIx)1632 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
1633 {
1634 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1635 }
1636
1637 /**
1638 * @brief Set NSS Mode
1639 * @note This configuration can not be changed when SPI is enabled.
1640 * This bit is not used in SPI TI mode.
1641 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1642 * CFG2 SSOE LL_SPI_SetNSSMode
1643 * @param SPIx SPI Instance
1644 * @param NSS This parameter can be one of the following values:
1645 * @arg @ref LL_SPI_NSS_SOFT
1646 * @arg @ref LL_SPI_NSS_HARD_INPUT
1647 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1648 * @retval None
1649 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)1650 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1651 {
1652 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1653 }
1654
1655 /**
1656 * @brief Set NSS Mode
1657 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1658 * CFG2 SSOE LL_SPI_GetNSSMode
1659 * @param SPIx SPI Instance
1660 * @retval Returned value can be one of the following values:
1661 * @arg @ref LL_SPI_NSS_SOFT
1662 * @arg @ref LL_SPI_NSS_HARD_INPUT
1663 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1664 */
LL_SPI_GetNSSMode(const SPI_TypeDef * SPIx)1665 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
1666 {
1667 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1668 }
1669
1670 /**
1671 * @brief Enable NSS pulse mgt
1672 * @note This configuration can not be changed when SPI is enabled.
1673 * This bit is not used in SPI TI mode.
1674 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1675 * @param SPIx SPI Instance
1676 * @retval None
1677 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)1678 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1679 {
1680 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1681 }
1682
1683 /**
1684 * @brief Disable NSS pulse mgt
1685 * @note This configuration can not be changed when SPI is enabled.
1686 * This bit is not used in SPI TI mode.
1687 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1688 * @param SPIx SPI Instance
1689 * @retval None
1690 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)1691 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1692 {
1693 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1694 }
1695
1696 /**
1697 * @brief Check if NSS pulse is enabled
1698 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1699 * @param SPIx SPI Instance
1700 * @retval State of bit (1 or 0)
1701 */
LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef * SPIx)1702 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
1703 {
1704 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1705 }
1706
1707 /**
1708 * @}
1709 */
1710
1711 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1712 * @{
1713 */
1714
1715 /**
1716 * @brief Check if there is enough data in FIFO to read a full packet
1717 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1718 * @param SPIx SPI Instance
1719 * @retval State of bit (1 or 0)
1720 */
LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef * SPIx)1721 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
1722 {
1723 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1724 }
1725
1726 /**
1727 * @brief Check if there is enough space in FIFO to hold a full packet
1728 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1729 * @param SPIx SPI Instance
1730 * @retval State of bit (1 or 0)
1731 */
LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef * SPIx)1732 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
1733 {
1734 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1735 }
1736
1737 /**
1738 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1739 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1740 * @param SPIx SPI Instance
1741 * @retval State of bit (1 or 0)
1742 */
LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef * SPIx)1743 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
1744 {
1745 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1746 }
1747
1748 /**
1749 * @brief Check that end of transfer event occurred
1750 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1751 * @param SPIx SPI Instance
1752 * @retval State of bit (1 or 0).
1753 */
LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef * SPIx)1754 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
1755 {
1756 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Check that all required data has been filled in the fifo according to transfer size
1761 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1762 * @param SPIx SPI Instance
1763 * @retval State of bit (1 or 0).
1764 */
LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef * SPIx)1765 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
1766 {
1767 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1768 }
1769
1770 /**
1771 * @brief Get Underrun error flag
1772 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1773 * @param SPIx SPI Instance
1774 * @retval State of bit (1 or 0).
1775 */
LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef * SPIx)1776 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1777 {
1778 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1779 }
1780
1781 /**
1782 * @brief Get CRC error flag
1783 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1784 * @param SPIx SPI Instance
1785 * @retval State of bit (1 or 0).
1786 */
LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef * SPIx)1787 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
1788 {
1789 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1790 }
1791
1792 /**
1793 * @brief Get Mode fault error flag
1794 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1795 * @param SPIx SPI Instance
1796 * @retval State of bit (1 or 0).
1797 */
LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef * SPIx)1798 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
1799 {
1800 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1801 }
1802
1803 /**
1804 * @brief Get Overrun error flag
1805 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1806 * @param SPIx SPI Instance
1807 * @retval State of bit (1 or 0).
1808 */
LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)1809 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1810 {
1811 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1812 }
1813
1814 /**
1815 * @brief Get TI Frame format error flag
1816 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1817 * @param SPIx SPI Instance
1818 * @retval State of bit (1 or 0).
1819 */
LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)1820 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
1821 {
1822 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1823 }
1824
1825 /**
1826 * @brief Check if a suspend operation is done
1827 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1828 * @param SPIx SPI Instance
1829 * @retval State of bit (1 or 0)
1830 */
LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef * SPIx)1831 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
1832 {
1833 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1834 }
1835
1836 /**
1837 * @brief Check if last TxFIFO or CRC frame transmission is completed
1838 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1839 * @param SPIx SPI Instance
1840 * @retval State of bit (1 or 0).
1841 */
LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef * SPIx)1842 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
1843 {
1844 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1845 }
1846
1847 /**
1848 * @brief Check if at least one 32-bit data is available in RxFIFO
1849 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1850 * @param SPIx SPI Instance
1851 * @retval State of bit (1 or 0)
1852 */
LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef * SPIx)1853 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
1854 {
1855 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1856 }
1857
1858 /**
1859 * @brief Get number of data framed remaining in current TSIZE
1860 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1861 * @param SPIx SPI Instance
1862 * @retval 0..0xFFFF
1863 */
LL_SPI_GetRemainingDataFrames(const SPI_TypeDef * SPIx)1864 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
1865 {
1866 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1867 }
1868
1869 /**
1870 * @brief Get RxFIFO packing Level
1871 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1872 * @param SPIx SPI Instance
1873 * @retval Returned value can be one of the following values:
1874 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1875 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1876 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1877 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1878 */
LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef * SPIx)1879 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
1880 {
1881 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1882 }
1883
1884 /**
1885 * @brief Clear End Of Transfer flag
1886 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1887 * @param SPIx SPI Instance
1888 * @retval None
1889 */
LL_SPI_ClearFlag_EOT(SPI_TypeDef * SPIx)1890 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1891 {
1892 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1893 }
1894
1895 /**
1896 * @brief Clear TXTF flag
1897 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1898 * @param SPIx SPI Instance
1899 * @retval None
1900 */
LL_SPI_ClearFlag_TXTF(SPI_TypeDef * SPIx)1901 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1902 {
1903 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1904 }
1905
1906 /**
1907 * @brief Clear Underrun error flag
1908 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1909 * @param SPIx SPI Instance
1910 * @retval None
1911 */
LL_SPI_ClearFlag_UDR(SPI_TypeDef * SPIx)1912 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1913 {
1914 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1915 }
1916
1917 /**
1918 * @brief Clear Overrun error flag
1919 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1920 * @param SPIx SPI Instance
1921 * @retval None
1922 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1923 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1924 {
1925 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1926 }
1927
1928 /**
1929 * @brief Clear CRC error flag
1930 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1931 * @param SPIx SPI Instance
1932 * @retval None
1933 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1934 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1935 {
1936 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1937 }
1938
1939 /**
1940 * @brief Clear Mode fault error flag
1941 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1942 * @param SPIx SPI Instance
1943 * @retval None
1944 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1945 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1946 {
1947 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1948 }
1949
1950 /**
1951 * @brief Clear Frame format error flag
1952 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1953 * @param SPIx SPI Instance
1954 * @retval None
1955 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1956 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1957 {
1958 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1959 }
1960
1961 /**
1962 * @brief Clear SUSP flag
1963 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1964 * @param SPIx SPI Instance
1965 * @retval None
1966 */
LL_SPI_ClearFlag_SUSP(SPI_TypeDef * SPIx)1967 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1968 {
1969 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1970 }
1971
1972 /**
1973 * @}
1974 */
1975
1976 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1977 * @{
1978 */
1979
1980 /**
1981 * @brief Enable Rx Packet available IT
1982 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1983 * @param SPIx SPI Instance
1984 * @retval None
1985 */
LL_SPI_EnableIT_RXP(SPI_TypeDef * SPIx)1986 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1987 {
1988 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1989 }
1990
1991 /**
1992 * @brief Enable Tx Packet space available IT
1993 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1994 * @param SPIx SPI Instance
1995 * @retval None
1996 */
LL_SPI_EnableIT_TXP(SPI_TypeDef * SPIx)1997 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1998 {
1999 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
2000 }
2001
2002 /**
2003 * @brief Enable Duplex Packet available IT
2004 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
2005 * @param SPIx SPI Instance
2006 * @retval None
2007 */
LL_SPI_EnableIT_DXP(SPI_TypeDef * SPIx)2008 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
2009 {
2010 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
2011 }
2012
2013 /**
2014 * @brief Enable End Of Transfer IT
2015 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
2016 * @param SPIx SPI Instance
2017 * @retval None
2018 */
LL_SPI_EnableIT_EOT(SPI_TypeDef * SPIx)2019 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
2020 {
2021 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
2022 }
2023
2024 /**
2025 * @brief Enable TXTF IT
2026 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
2027 * @param SPIx SPI Instance
2028 * @retval None
2029 */
LL_SPI_EnableIT_TXTF(SPI_TypeDef * SPIx)2030 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
2031 {
2032 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
2033 }
2034
2035 /**
2036 * @brief Enable Underrun IT
2037 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
2038 * @param SPIx SPI Instance
2039 * @retval None
2040 */
LL_SPI_EnableIT_UDR(SPI_TypeDef * SPIx)2041 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
2042 {
2043 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
2044 }
2045
2046 /**
2047 * @brief Enable Overrun IT
2048 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
2049 * @param SPIx SPI Instance
2050 * @retval None
2051 */
LL_SPI_EnableIT_OVR(SPI_TypeDef * SPIx)2052 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
2053 {
2054 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
2055 }
2056
2057 /**
2058 * @brief Enable CRC Error IT
2059 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
2060 * @param SPIx SPI Instance
2061 * @retval None
2062 */
LL_SPI_EnableIT_CRCERR(SPI_TypeDef * SPIx)2063 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
2064 {
2065 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
2066 }
2067
2068 /**
2069 * @brief Enable TI Frame Format Error IT
2070 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
2071 * @param SPIx SPI Instance
2072 * @retval None
2073 */
LL_SPI_EnableIT_FRE(SPI_TypeDef * SPIx)2074 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
2075 {
2076 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
2077 }
2078
2079 /**
2080 * @brief Enable MODF IT
2081 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
2082 * @param SPIx SPI Instance
2083 * @retval None
2084 */
LL_SPI_EnableIT_MODF(SPI_TypeDef * SPIx)2085 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
2086 {
2087 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2088 }
2089
2090 /**
2091 * @brief Disable Rx Packet available IT
2092 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2093 * @param SPIx SPI Instance
2094 * @retval None
2095 */
LL_SPI_DisableIT_RXP(SPI_TypeDef * SPIx)2096 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2097 {
2098 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2099 }
2100
2101 /**
2102 * @brief Disable Tx Packet space available IT
2103 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2104 * @param SPIx SPI Instance
2105 * @retval None
2106 */
LL_SPI_DisableIT_TXP(SPI_TypeDef * SPIx)2107 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2108 {
2109 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2110 }
2111
2112 /**
2113 * @brief Disable Duplex Packet available IT
2114 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2115 * @param SPIx SPI Instance
2116 * @retval None
2117 */
LL_SPI_DisableIT_DXP(SPI_TypeDef * SPIx)2118 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2119 {
2120 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2121 }
2122
2123 /**
2124 * @brief Disable End Of Transfer IT
2125 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2126 * @param SPIx SPI Instance
2127 * @retval None
2128 */
LL_SPI_DisableIT_EOT(SPI_TypeDef * SPIx)2129 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2130 {
2131 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2132 }
2133
2134 /**
2135 * @brief Disable TXTF IT
2136 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2137 * @param SPIx SPI Instance
2138 * @retval None
2139 */
LL_SPI_DisableIT_TXTF(SPI_TypeDef * SPIx)2140 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2141 {
2142 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2143 }
2144
2145 /**
2146 * @brief Disable Underrun IT
2147 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2148 * @param SPIx SPI Instance
2149 * @retval None
2150 */
LL_SPI_DisableIT_UDR(SPI_TypeDef * SPIx)2151 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2152 {
2153 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2154 }
2155
2156 /**
2157 * @brief Disable Overrun IT
2158 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2159 * @param SPIx SPI Instance
2160 * @retval None
2161 */
LL_SPI_DisableIT_OVR(SPI_TypeDef * SPIx)2162 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2163 {
2164 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2165 }
2166
2167 /**
2168 * @brief Disable CRC Error IT
2169 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2170 * @param SPIx SPI Instance
2171 * @retval None
2172 */
LL_SPI_DisableIT_CRCERR(SPI_TypeDef * SPIx)2173 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2174 {
2175 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2176 }
2177
2178 /**
2179 * @brief Disable TI Frame Format Error IT
2180 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2181 * @param SPIx SPI Instance
2182 * @retval None
2183 */
LL_SPI_DisableIT_FRE(SPI_TypeDef * SPIx)2184 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2185 {
2186 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2187 }
2188
2189 /**
2190 * @brief Disable MODF IT
2191 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2192 * @param SPIx SPI Instance
2193 * @retval None
2194 */
LL_SPI_DisableIT_MODF(SPI_TypeDef * SPIx)2195 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2196 {
2197 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2198 }
2199
2200 /**
2201 * @brief Check if Rx Packet available IT is enabled
2202 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2203 * @param SPIx SPI Instance
2204 * @retval State of bit (1 or 0)
2205 */
LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef * SPIx)2206 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
2207 {
2208 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2209 }
2210
2211 /**
2212 * @brief Check if Tx Packet space available IT is enabled
2213 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2214 * @param SPIx SPI Instance
2215 * @retval State of bit (1 or 0)
2216 */
LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef * SPIx)2217 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
2218 {
2219 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2220 }
2221
2222 /**
2223 * @brief Check if Duplex Packet available IT is enabled
2224 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2225 * @param SPIx SPI Instance
2226 * @retval State of bit (1 or 0)
2227 */
LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef * SPIx)2228 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
2229 {
2230 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2231 }
2232
2233 /**
2234 * @brief Check if End Of Transfer IT is enabled
2235 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2236 * @param SPIx SPI Instance
2237 * @retval State of bit (1 or 0)
2238 */
LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef * SPIx)2239 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
2240 {
2241 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2242 }
2243
2244 /**
2245 * @brief Check if TXTF IT is enabled
2246 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2247 * @param SPIx SPI Instance
2248 * @retval State of bit (1 or 0)
2249 */
LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef * SPIx)2250 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
2251 {
2252 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2253 }
2254
2255 /**
2256 * @brief Check if Underrun IT is enabled
2257 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2258 * @param SPIx SPI Instance
2259 * @retval State of bit (1 or 0)
2260 */
LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef * SPIx)2261 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
2262 {
2263 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2264 }
2265
2266 /**
2267 * @brief Check if Overrun IT is enabled
2268 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2269 * @param SPIx SPI Instance
2270 * @retval State of bit (1 or 0)
2271 */
LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef * SPIx)2272 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
2273 {
2274 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2275 }
2276
2277 /**
2278 * @brief Check if CRC Error IT is enabled
2279 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2280 * @param SPIx SPI Instance
2281 * @retval State of bit (1 or 0)
2282 */
LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef * SPIx)2283 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
2284 {
2285 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2286 }
2287
2288 /**
2289 * @brief Check if TI Frame Format Error IT is enabled
2290 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2291 * @param SPIx SPI Instance
2292 * @retval State of bit (1 or 0)
2293 */
LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef * SPIx)2294 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
2295 {
2296 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2297 }
2298
2299 /**
2300 * @brief Check if MODF IT is enabled
2301 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2302 * @param SPIx SPI Instance
2303 * @retval State of bit (1 or 0)
2304 */
LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef * SPIx)2305 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
2306 {
2307 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2308 }
2309
2310 /**
2311 * @}
2312 */
2313
2314 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
2315 * @{
2316 */
2317
2318 /**
2319 * @brief Enable DMA Rx
2320 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2321 * @param SPIx SPI Instance
2322 * @retval None
2323 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)2324 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2325 {
2326 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2327 }
2328
2329 /**
2330 * @brief Disable DMA Rx
2331 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2332 * @param SPIx SPI Instance
2333 * @retval None
2334 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)2335 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2336 {
2337 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2338 }
2339
2340 /**
2341 * @brief Check if DMA Rx is enabled
2342 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2343 * @param SPIx SPI Instance
2344 * @retval State of bit (1 or 0)
2345 */
LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)2346 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
2347 {
2348 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2349 }
2350
2351 /**
2352 * @brief Enable DMA Tx
2353 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2354 * @param SPIx SPI Instance
2355 * @retval None
2356 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)2357 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2358 {
2359 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2360 }
2361
2362 /**
2363 * @brief Disable DMA Tx
2364 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2365 * @param SPIx SPI Instance
2366 * @retval None
2367 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)2368 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2369 {
2370 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2371 }
2372
2373 /**
2374 * @brief Check if DMA Tx is enabled
2375 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2376 * @param SPIx SPI Instance
2377 * @retval State of bit (1 or 0)
2378 */
LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)2379 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
2380 {
2381 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2382 }
2383 /**
2384 * @brief Get the data register address used for DMA transfer
2385 * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr
2386 * @param SPIx SPI Instance
2387 * @retval Address of data register
2388 */
LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef * SPIx)2389 __STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
2390 {
2391 return (uint32_t) &(SPIx->TXDR);
2392 }
2393
2394 /**
2395 * @brief Get the data register address used for DMA transfer
2396 * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr
2397 * @param SPIx SPI Instance
2398 * @retval Address of data register
2399 */
LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef * SPIx)2400 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
2401 {
2402 return (uint32_t) &(SPIx->RXDR);
2403 }
2404 /**
2405 * @}
2406 */
2407
2408 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2409 * @{
2410 */
2411
2412 /**
2413 * @brief Read Data Register
2414 * @rmtoll RXDR . LL_SPI_ReceiveData8
2415 * @param SPIx SPI Instance
2416 * @retval 0..0xFF
2417 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)2418 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2419 {
2420 return (*((__IO uint8_t *)&SPIx->RXDR));
2421 }
2422
2423 /**
2424 * @brief Read Data Register
2425 * @rmtoll RXDR . LL_SPI_ReceiveData16
2426 * @param SPIx SPI Instance
2427 * @retval 0..0xFFFF
2428 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)2429 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2430 {
2431 #if defined (__GNUC__)
2432 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2433 return (*spirxdr);
2434 #else
2435 return (*((__IO uint16_t *)&SPIx->RXDR));
2436 #endif /* __GNUC__ */
2437 }
2438
2439 /**
2440 * @brief Read Data Register
2441 * @rmtoll RXDR . LL_SPI_ReceiveData32
2442 * @param SPIx SPI Instance
2443 * @retval 0..0xFFFFFFFF
2444 */
LL_SPI_ReceiveData32(SPI_TypeDef * SPIx)2445 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
2446 {
2447 return (*((__IO uint32_t *)&SPIx->RXDR));
2448 }
2449
2450 /**
2451 * @brief Write Data Register
2452 * @rmtoll TXDR . LL_SPI_TransmitData8
2453 * @param SPIx SPI Instance
2454 * @param TxData 0..0xFF
2455 * @retval None
2456 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)2457 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2458 {
2459 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2460 }
2461
2462 /**
2463 * @brief Write Data Register
2464 * @rmtoll TXDR . LL_SPI_TransmitData16
2465 * @param SPIx SPI Instance
2466 * @param TxData 0..0xFFFF
2467 * @retval None
2468 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)2469 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2470 {
2471 #if defined (__GNUC__)
2472 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2473 *spitxdr = TxData;
2474 #else
2475 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2476 #endif /* __GNUC__ */
2477 }
2478
2479 /**
2480 * @brief Write Data Register
2481 * @rmtoll TXDR . LL_SPI_TransmitData32
2482 * @param SPIx SPI Instance
2483 * @param TxData 0..0xFFFFFFFF
2484 * @retval None
2485 */
LL_SPI_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)2486 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2487 {
2488 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2489 }
2490
2491 /**
2492 * @brief Set polynomial for CRC calcul
2493 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2494 * @param SPIx SPI Instance
2495 * @param CRCPoly 0..0xFFFFFFFF
2496 * @retval None
2497 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)2498 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2499 {
2500 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2501 }
2502
2503 /**
2504 * @brief Get polynomial for CRC calcul
2505 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2506 * @param SPIx SPI Instance
2507 * @retval 0..0xFFFFFFFF
2508 */
LL_SPI_GetCRCPolynomial(const SPI_TypeDef * SPIx)2509 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
2510 {
2511 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2512 }
2513
2514 /**
2515 * @brief Set the underrun pattern
2516 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2517 * @param SPIx SPI Instance
2518 * @param Pattern 0..0xFFFFFFFF
2519 * @retval None
2520 */
LL_SPI_SetUDRPattern(SPI_TypeDef * SPIx,uint32_t Pattern)2521 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2522 {
2523 WRITE_REG(SPIx->UDRDR, Pattern);
2524 }
2525
2526 /**
2527 * @brief Get the underrun pattern
2528 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2529 * @param SPIx SPI Instance
2530 * @retval 0..0xFFFFFFFF
2531 */
LL_SPI_GetUDRPattern(const SPI_TypeDef * SPIx)2532 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
2533 {
2534 return (uint32_t)(READ_REG(SPIx->UDRDR));
2535 }
2536
2537 /**
2538 * @brief Get Rx CRC
2539 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2540 * @param SPIx SPI Instance
2541 * @retval 0..0xFFFFFFFF
2542 */
LL_SPI_GetRxCRC(const SPI_TypeDef * SPIx)2543 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
2544 {
2545 return (uint32_t)(READ_REG(SPIx->RXCRC));
2546 }
2547
2548 /**
2549 * @brief Get Tx CRC
2550 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2551 * @param SPIx SPI Instance
2552 * @retval 0..0xFFFFFFFF
2553 */
LL_SPI_GetTxCRC(const SPI_TypeDef * SPIx)2554 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
2555 {
2556 return (uint32_t)(READ_REG(SPIx->TXCRC));
2557 }
2558
2559 /**
2560 * @}
2561 */
2562
2563 /** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature
2564 * @{
2565 */
2566
2567 /**
2568 * @brief Enable Selected Trigger
2569 * @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger
2570 * @param SPIx SPI Instance.
2571 * @retval None
2572 */
LL_SPI_Enable_SelectedTrigger(SPI_TypeDef * SPIx)2573 __STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx)
2574 {
2575 SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
2576 }
2577
2578 /**
2579 * @brief Disable Selected Trigger
2580 * @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger
2581 * @param SPIx SPI Instance.
2582 * @retval None
2583 */
LL_SPI_Disable_SelectedTrigger(SPI_TypeDef * SPIx)2584 __STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx)
2585 {
2586 CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
2587 }
2588
2589 /**
2590 * @brief Indicate if selected Trigger is disabled or enabled
2591 * @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger
2592 * @param SPIx SPI Instance.
2593 * @retval State of bit (1 or 0).
2594 */
LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef * SPIx)2595 __STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef *SPIx)
2596 {
2597 return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL);
2598 }
2599
2600 /**
2601 * @brief Set the trigger polarity
2602 * @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity
2603 * @param SPIx SPI Instance.
2604 * @param Polarity This parameter can be one of the following values:
2605 * @arg @ref LL_SPI_TRIG_POLARITY_RISING
2606 * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
2607 * @retval None
2608 */
LL_SPI_SetTriggerPolarity(SPI_TypeDef * SPIx,uint32_t Polarity)2609 __STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity)
2610 {
2611 MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity);
2612 }
2613
2614 /**
2615 * @brief Get the trigger polarity
2616 * @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity
2617 * @param SPIx SPI Instance.
2618 * @retval Returned value can be one of the following values:
2619 * @arg @ref LL_SPI_TRIG_POLARITY_RISING
2620 * @arg @ref LL_SPI_TRIG_POLARITY_FALLING
2621 */
LL_SPI_GetTriggerPolarity(const SPI_TypeDef * SPIx)2622 __STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(const SPI_TypeDef *SPIx)
2623 {
2624 return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL));
2625 }
2626
2627 /**
2628 * @brief Set the selected trigger
2629 * @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger
2630 * @param SPIx SPI Instance.
2631 * @param Trigger This parameter can be one of the following values:
2632 * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
2633 * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
2634 * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
2635 * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
2636 * @arg @ref LL_SPI_GRP1_EXTI4_TRG
2637 * @arg @ref LL_SPI_GRP1_EXTI9_TRG
2638 * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
2639 * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
2640 * @arg @ref LL_SPI_GRP1_COMP1_TRG
2641 * @arg @ref LL_SPI_GRP1_COMP2_TRG
2642 * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
2643 * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
2644 * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG
2645 * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG
2646 * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG
2647 * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG
2648 * @arg @ref LL_SPI_GRP2_EXTI4_TRG
2649 * @arg @ref LL_SPI_GRP2_EXTI8_TRG
2650 * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
2651 * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG
2652 * @arg @ref LL_SPI_GRP2_COMP1_TRG
2653 * @arg @ref LL_SPI_GRP2_COMP2_TRG
2654 * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
2655 * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
2656 * @retval None
2657 */
LL_SPI_SetSelectedTrigger(SPI_TypeDef * SPIx,uint32_t Trigger)2658 __STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger)
2659 {
2660 MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk));
2661 }
2662
2663 /**
2664 * @brief Get the selected trigger
2665 * @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger
2666 * @param SPIx SPI Instance.
2667 * @retval Returned value can be one of the following values:
2668 * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
2669 * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
2670 * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
2671 * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
2672 * @arg @ref LL_SPI_GRP1_EXTI4_TRG
2673 * @arg @ref LL_SPI_GRP1_EXTI9_TRG
2674 * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
2675 * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
2676 * @arg @ref LL_SPI_GRP1_COMP1_TRG
2677 * @arg @ref LL_SPI_GRP1_COMP2_TRG
2678 * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
2679 * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
2680 * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG
2681 * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG
2682 * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG
2683 * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG
2684 * @arg @ref LL_SPI_GRP2_EXTI4_TRG
2685 * @arg @ref LL_SPI_GRP2_EXTI8_TRG
2686 * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
2687 * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG
2688 * @arg @ref LL_SPI_GRP2_COMP1_TRG
2689 * @arg @ref LL_SPI_GRP2_COMP2_TRG
2690 * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
2691 * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
2692 */
LL_SPI_GetSelectedTrigger(const SPI_TypeDef * SPIx)2693 __STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(const SPI_TypeDef *SPIx)
2694 {
2695 #if defined(LL_SPI_TRIG_GRP2)
2696 if (IS_LL_SPI_GRP2_INSTANCE(SPIx))
2697 {
2698 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2));
2699 }
2700 else
2701 {
2702 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1));
2703 }
2704 #else
2705 return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1));
2706 #endif /* LL_SPI_TRIG_GRP2 */
2707 }
2708
2709 /**
2710 * @}
2711 */
2712
2713 #if defined(USE_FULL_LL_DRIVER)
2714 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2715 * @{
2716 */
2717
2718 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
2719 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2720 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2721
2722 /**
2723 * @}
2724 */
2725 #endif /* USE_FULL_LL_DRIVER */
2726 /**
2727 * @}
2728 */
2729 /**
2730 * @}
2731 */
2732
2733
2734 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */
2735
2736 /**
2737 * @}
2738 */
2739
2740 #ifdef __cplusplus
2741 }
2742 #endif
2743
2744 #endif /* STM32U5xx_LL_SPI_H */
2745
