1021   MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);  in LL_SPI_SetUDRConfiguration()
1034   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));  in LL_SPI_GetUDRConfiguration()
1174   MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);  in LL_SPI_SetBaudRatePrescaler()
1195   return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));  in LL_SPI_GetBaudRatePrescaler()
1335   MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);  in LL_SPI_SetDataWidth()
1375   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));  in LL_SPI_GetDataWidth()
1404   MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);  in LL_SPI_SetFIFOThreshold()
1431   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));  in LL_SPI_GetFIFOThreshold()
1443   SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);  in LL_SPI_EnableCRC()
1454   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);  in LL_SPI_DisableCRC()
1465   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);  in LL_SPI_IsEnabledCRC()
1507   MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);  in LL_SPI_SetCRCWidth()
1547   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));  in LL_SPI_GetCRCWidth()
2239   SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);  in LL_SPI_EnableDMAReq_RX()
2250   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);  in LL_SPI_DisableDMAReq_RX()
2261   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);  in LL_SPI_IsEnabledDMAReq_RX()
2272   SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);  in LL_SPI_EnableDMAReq_TX()
2283   CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);  in LL_SPI_DisableDMAReq_TX()
2294   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);  in LL_SPI_IsEnabledDMAReq_TX()