1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_ucpd.h
4 * @author MCD Application Team
5 * @brief Header file of UCPD LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32N6xx_LL_UCPD_H
21 #define STM32N6xx_LL_UCPD_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29
30 /** @addtogroup STM32N6xx_LL_Driver
31 * @{
32 */
33
34 #if defined (UCPD1)
35
36 /** @defgroup UCPD_LL UCPD
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43
44 /* Exported types ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
47 * @{
48 */
49
50 /**
51 * @brief UCPD Init structures definition
52 */
53 typedef struct
54 {
55 uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock.
56 This parameter can be a value of @ref UCPD_LL_EC_PSC.
57 This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
58 */
59
60 uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
61 to achieve a legal tTransitionWindow (set according to peripheral clock to define
62 an interval of between 12 and 20 us).
63 This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
64 This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
65 */
66
67 uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate
68 tInterframeGap from the peripheral clock.
69 This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
70 This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
71 */
72
73 uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
74 e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
75 "UCPD1_CLK".
76 This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
77 This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
78 */
79
80 } LL_UCPD_InitTypeDef;
81
82 /**
83 * @}
84 */
85 #endif /* USE_FULL_LL_DRIVER */
86
87 /* Exported constants --------------------------------------------------------*/
88 /** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
89 * @{
90 */
91
92 /** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
93 * @brief Flags defines which can be used with LL_ucpd_ReadReg function
94 * @{
95 */
96 #define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
97 #define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
98 #define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
99 #define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
100 #define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
101 #define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
102 #define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
103 #define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
104 #define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
105 #define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
106 #define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
107 #define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
108 #define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
109 #define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
110 #define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
111 #define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!<Status of DC level on CC1 pin */
112 #define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 /*!<Status of DC level on CC2 pin */
113
114 /**
115 * @}
116 */
117
118 /** @defgroup UCPD_LL_EC_IT IT Defines
119 * @brief IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions
120 * @{
121 */
122 #define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE /*!< Enable transmit interrupt status */
123 #define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE /*!< Enable transmit message discarded interrupt */
124 #define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE /*!< Enable transmit message sent interrupt */
125 #define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE /*!< Enable transmit message abort interrupt */
126 #define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE /*!< Enable HRST discarded interrupt */
127 #define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE /*!< Enable HRST sent interrupt */
128 #define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE /*!< Enable tx data underrun condition interrupt */
129 #define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE /*!< Enable Receive data register not empty interrupt */
130 #define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
131 #define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
132 #define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
133 #define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE /*!< Enable Rx message received */
134 #define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
135 #define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
136
137 /**
138 * @}
139 */
140
141 /** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
142 * @brief definition of the usual Ordered sets
143 * @{
144 */
145 #define LL_UCPD_SYNC1 0x18u /*!< K-code for Startsynch #1 */
146 #define LL_UCPD_SYNC2 0x11u /*!< K-code for Startsynch #2 */
147 #define LL_UCPD_SYNC3 0x06u /*!< K-code for Startsynch #3 */
148 #define LL_UCPD_RST1 0x07u /*!< K-code for Hard Reset #1 */
149 #define LL_UCPD_RST2 0x19u /*!< K-code for Hard Reset #2 */
150 #define LL_UCPD_EOP 0x0Du /*!< K-code for EOP End of Packet */
151
152 #define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding */
153 #define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding */
154 #define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding */
155 #define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding */
156 #define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
157 #define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding */
158 #define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
159 /**
160 * @}
161 */
162
163 /** @defgroup UCPD_LL_EC_MODE Role Mode
164 * @{
165 */
166 #define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE /*!< Mode SNK Rd */
167 #define LL_UCPD_ROLE_SRC 0x0U /*!< Mode SRC Rp */
168 /**
169 * @}
170 */
171
172 /** @defgroup UCPD_LL_EC_RESISTOR Resistor value
173 * @{
174 */
175 #define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 /*!< Rp default */
176 #define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 /*!< Rp 1.5 A */
177 #define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE /*!< Rp 3.0 A */
178 #define LL_UCPD_RESISTOR_NONE 0x0U /*!< No resistor */
179 /**
180 * @}
181 */
182
183 /** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
184 * @{
185 */
186 #define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0 /*!< SOP Ordered set detection enabled */
187 #define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1 /*!< SOP' Ordered set detection enabled */
188 #define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2 /*!< SOP'' Ordered set detection enabled */
189 #define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3 /*!< Hard Reset Ordered set detection enabled */
190 #define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4 /*!< Cable Reset Ordered set detection enabled */
191 #define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5 /*!< SOP' Debug Ordered set detection enabled */
192 #define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6 /*!< SOP'' Debug Ordered set detection enabled */
193 #define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7 /*!< SOP extension#1 Ordered set detection enabled */
194 #define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8 /*!< SOP extension#2 Ordered set detection enabled */
195 /**
196 * @}
197 */
198
199 /** @defgroup UCPD_LL_EC_CCxEVT CCx event
200 * @{
201 */
202 #define LL_UCPD_SNK_CC1_VOPEN 0x00u /*!< CC1 Sink Open state */
203 #define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Sink vRP default state */
204 #define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Sink vRP 1.5A state */
205 #define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1) /*!< CC1 Sink vRP 3.0A state */
206
207 #define LL_UCPD_SNK_CC2_VOPEN 0x00u /*!< CC2 Sink Open state */
208 #define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Sink vRP default state */
209 #define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Sink vRP 1.5A state */
210 #define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1) /*!< CC2 Sink vRP 3.0A state */
211
212 #define LL_UCPD_SRC_CC1_VRA 0x0U /*!< CC1 Source vRA state */
213 #define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Source vRD state */
214 #define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Source Open state */
215
216 #define LL_UCPD_SRC_CC2_VRA 0x0U /*!< CC2 Source vRA state */
217 #define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Source vRD state */
218 #define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Source Open state */
219 /**
220 * @}
221 */
222
223 /** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
224 * @{
225 */
226 #define LL_UCPD_PSC_DIV1 0x0u /*!< Bypass pre-scaling / divide by 1 */
227 #define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0 /*!< Pre-scale clock by dividing by 2 */
228 #define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1 /*!< Pre-scale clock by dividing by 4 */
229 #define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0) /*!< Pre-scale clock by dividing by 8 */
230 #define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2 /*!< Pre-scale clock by dividing by 16 */
231 /**
232 * @}
233 */
234
235 /** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
236 * @{
237 */
238 #define LL_UCPD_CCENABLE_NONE 0x0U /*!< Neither PHY is activated (e.g. disabled state of source) */
239 #define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0 /*!< Controls apply to only CC1 */
240 #define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1 /*!< Controls apply to only CC1 */
241 #define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1) /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
242 /**
243 * @}
244 */
245
246 /** @defgroup UCPD_LL_EC_CCPIN CC pin selection
247 * @{
248 */
249 #define LL_UCPD_CCPIN_CC1 0x0U /*!< Use CC1 IO for power delivery communication */
250 #define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL /*!< Use CC2 IO for power delivery communication */
251 /**
252 * @}
253 */
254
255 /** @defgroup UCPD_LL_EC_RXMODE Receiver mode
256 * @{
257 */
258 #define LL_UCPD_RXMODE_NORMAL 0x0U /*!< Normal receive mode */
259 #define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE /*!< BIST receive mode (BIST Test Data Mode) */
260 /**
261 * @}
262 */
263
264 /** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
265 * @{
266 */
267 #define LL_UCPD_TXMODE_NORMAL 0x0U /*!< Initiate the transfer of a Tx message */
268 #define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0 /*!< Trigger a the transfer of a Cable Reset sequence */
269 #define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1 /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2) */
270 /**
271 * @}
272 */
273
274 /** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
275 * @{
276 */
277 #define LL_UCPD_RXORDSET_SOP 0x0U /*!< SOP code detected in receiver */
278 #define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0 /*!< SOP' code detected in receiver */
279 #define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1 /*!< SOP'' code detected in receiver */
280 #define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP' Debug code detected in receiver */
281 #define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2 /*!< SOP'' Debug code detected in receiver */
282 #define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0) /*!< Cable Reset code detected in receiver */
283 #define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP extension#1 code detected in receiver */
284 #define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0) /*!< SOP extension#2 code detected in receiver */
285 /**
286 * @}
287 */
288
289 /**
290 * @}
291 */
292
293 /* Exported macro ------------------------------------------------------------*/
294 /** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
295 * @{
296 */
297
298 /** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
299 * @{
300 */
301
302 /**
303 * @brief Write a value in UCPD register
304 * @param __INSTANCE__ UCPD Instance
305 * @param __REG__ Register to be written
306 * @param __VALUE__ Value to be written in the register
307 * @retval None
308 */
309 #define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
310
311 /**
312 * @brief Read a value in UCPD register
313 * @param __INSTANCE__ UCPD Instance
314 * @param __REG__ Register to be read
315 * @retval Register value
316 */
317 #define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
318 /**
319 * @}
320 */
321
322 /**
323 * @}
324 */
325
326 /* Exported functions --------------------------------------------------------*/
327 /** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
328 * @{
329 */
330
331 /** @defgroup UCPD_LL_EF_Configuration Configuration
332 * @{
333 */
334
335 /** @defgroup UCPD_LL_EF_CFG1 CFG1 register
336 * @{
337 */
338 /**
339 * @brief Enable UCPD peripheral
340 * @rmtoll CFG1 UCPDEN LL_UCPD_Enable
341 * @param UCPDx UCPD Instance
342 * @retval None
343 */
LL_UCPD_Enable(UCPD_TypeDef * UCPDx)344 __STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
345 {
346 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
347 }
348
349 /**
350 * @brief Disable UCPD peripheral
351 * @note When disabling the UCPD, follow the procedure described in the Reference Manual.
352 * @rmtoll CFG1 UCPDEN LL_UCPD_Disable
353 * @param UCPDx UCPD Instance
354 * @retval None
355 */
LL_UCPD_Disable(UCPD_TypeDef * UCPDx)356 __STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
357 {
358 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
359 }
360
361 /**
362 * @brief Check if UCPD peripheral is enabled
363 * @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled
364 * @param UCPDx UCPD Instance
365 * @retval State of bit (1 or 0).
366 */
LL_UCPD_IsEnabled(UCPD_TypeDef const * const UCPDx)367 __STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
368 {
369 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
370 }
371
372 /**
373 * @brief Set the receiver ordered set detection enable
374 * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
375 * @param UCPDx UCPD Instance
376 * @param OrderSet This parameter can be combination of the following values:
377 * @arg @ref LL_UCPD_ORDERSET_SOP
378 * @arg @ref LL_UCPD_ORDERSET_SOP1
379 * @arg @ref LL_UCPD_ORDERSET_SOP2
380 * @arg @ref LL_UCPD_ORDERSET_HARDRST
381 * @arg @ref LL_UCPD_ORDERSET_CABLERST
382 * @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
383 * @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
384 * @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
385 * @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
386 * @retval None
387 */
LL_UCPD_SetRxOrderSet(UCPD_TypeDef * UCPDx,uint32_t OrderSet)388 __STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
389 {
390 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
391 }
392
393 /**
394 * @brief Set the prescaler for ucpd clock
395 * @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk
396 * @param UCPDx UCPD Instance
397 * @param Psc This parameter can be one of the following values:
398 * @arg @ref LL_UCPD_PSC_DIV1
399 * @arg @ref LL_UCPD_PSC_DIV2
400 * @arg @ref LL_UCPD_PSC_DIV4
401 * @arg @ref LL_UCPD_PSC_DIV8
402 * @arg @ref LL_UCPD_PSC_DIV16
403 * @retval None
404 */
LL_UCPD_SetPSCClk(UCPD_TypeDef * UCPDx,uint32_t Psc)405 __STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
406 {
407 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
408 }
409
410 /**
411 * @brief Set the number of cycles (minus 1) of the half bit clock
412 * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin
413 * @param UCPDx UCPD Instance
414 * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F
415 * @retval None
416 */
LL_UCPD_SetTransWin(UCPD_TypeDef * UCPDx,uint32_t TransWin)417 __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
418 {
419 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
420 }
421
422 /**
423 * @brief Set the clock divider value to generate an interframe gap
424 * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap
425 * @param UCPDx UCPD Instance
426 * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
427 * @retval None
428 */
LL_UCPD_SetIfrGap(UCPD_TypeDef * UCPDx,uint32_t IfrGap)429 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
430 {
431 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
432 }
433
434 /**
435 * @brief Set the clock divider value to generate an interframe gap
436 * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
437 * @param UCPDx UCPD Instance
438 * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
439 * @retval None
440 */
LL_UCPD_SetHbitClockDiv(UCPD_TypeDef * UCPDx,uint32_t HbitClock)441 __STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
442 {
443 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
444 }
445
446 /**
447 * @}
448 */
449
450 /** @defgroup UCPD_LL_EF_CFG2 CFG2 register
451 * @{
452 */
453
454 /**
455 * @brief Enable Rx Analog Filter
456 * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterEnable
457 * @param UCPDx UCPD Instance
458 * @retval None
459 */
LL_UCPD_RxAnalogFilterEnable(UCPD_TypeDef * UCPDx)460 __STATIC_INLINE void LL_UCPD_RxAnalogFilterEnable(UCPD_TypeDef *UCPDx)
461 {
462 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
463 }
464
465 /**
466 * @brief Disable Rx Analog Filter
467 * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterDisable
468 * @param UCPDx UCPD Instance
469 * @retval None
470 */
LL_UCPD_RxAnalogFilterDisable(UCPD_TypeDef * UCPDx)471 __STATIC_INLINE void LL_UCPD_RxAnalogFilterDisable(UCPD_TypeDef *UCPDx)
472 {
473 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
474 }
475
476 /**
477 * @brief Enable the wakeup mode
478 * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable
479 * @param UCPDx UCPD Instance
480 * @retval None
481 */
LL_UCPD_WakeUpEnable(UCPD_TypeDef * UCPDx)482 __STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
483 {
484 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
485 }
486
487 /**
488 * @brief Disable the wakeup mode
489 * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable
490 * @param UCPDx UCPD Instance
491 * @retval None
492 */
LL_UCPD_WakeUpDisable(UCPD_TypeDef * UCPDx)493 __STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
494 {
495 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
496 }
497
498 /**
499 * @brief Force clock enable
500 * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable
501 * @param UCPDx UCPD Instance
502 * @retval None
503 */
LL_UCPD_ForceClockEnable(UCPD_TypeDef * UCPDx)504 __STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
505 {
506 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
507 }
508
509 /**
510 * @brief Force clock disable
511 * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable
512 * @param UCPDx UCPD Instance
513 * @retval None
514 */
LL_UCPD_ForceClockDisable(UCPD_TypeDef * UCPDx)515 __STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
516 {
517 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
518 }
519
520 /**
521 * @brief RxFilter enable
522 * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
523 * @param UCPDx UCPD Instance
524 * @retval None
525 */
LL_UCPD_RxFilterEnable(UCPD_TypeDef * UCPDx)526 __STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
527 {
528 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
529 }
530
531 /**
532 * @brief RxFilter disable
533 * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
534 * @param UCPDx UCPD Instance
535 * @retval None
536 */
LL_UCPD_RxFilterDisable(UCPD_TypeDef * UCPDx)537 __STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
538 {
539 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
540 }
541
542 /**
543 * @}
544 */
545
546 /**
547 * @}
548 */
549
550 /** @defgroup UCPD_LL_EF_CR CR register
551 * @{
552 */
553 /**
554 * @brief Type C detector for CC2 enable
555 * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
556 * @param UCPDx UCPD Instance
557 * @retval None
558 */
LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef * UCPDx)559 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
560 {
561 CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
562 }
563
564 /**
565 * @brief Type C detector for CC2 disable
566 * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
567 * @param UCPDx UCPD Instance
568 * @retval None
569 */
LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef * UCPDx)570 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
571 {
572 SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
573 }
574
575 /**
576 * @brief Type C detector for CC1 enable
577 * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
578 * @param UCPDx UCPD Instance
579 * @retval None
580 */
LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef * UCPDx)581 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
582 {
583 CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
584 }
585
586 /**
587 * @brief Type C detector for CC1 disable
588 * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
589 * @param UCPDx UCPD Instance
590 * @retval None
591 */
LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef * UCPDx)592 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
593 {
594 SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
595 }
596
597 /**
598 * @brief Source Vconn discharge enable
599 * @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable
600 * @param UCPDx UCPD Instance
601 * @retval None
602 */
LL_UCPD_VconnDischargeEnable(UCPD_TypeDef * UCPDx)603 __STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
604 {
605 SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
606 }
607
608 /**
609 * @brief Source Vconn discharge disable
610 * @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable
611 * @param UCPDx UCPD Instance
612 * @retval None
613 */
LL_UCPD_VconnDischargeDisable(UCPD_TypeDef * UCPDx)614 __STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
615 {
616 CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
617 }
618
619 /**
620 * @brief Signal Fast Role Swap request
621 * @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable
622 * @param UCPDx UCPD Instance
623 * @retval None
624 */
LL_UCPD_SignalFRSTX(UCPD_TypeDef * UCPDx)625 __STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
626 {
627 SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
628 }
629
630 /**
631 * @brief Set cc enable
632 * @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable
633 * @param UCPDx UCPD Instance
634 * @param CCEnable This parameter can be one of the following values:
635 * @arg @ref LL_UCPD_CCENABLE_NONE
636 * @arg @ref LL_UCPD_CCENABLE_CC1
637 * @arg @ref LL_UCPD_CCENABLE_CC2
638 * @arg @ref LL_UCPD_CCENABLE_CC1CC2
639 * @retval None
640 */
LL_UCPD_SetccEnable(UCPD_TypeDef * UCPDx,uint32_t CCEnable)641 __STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
642 {
643 MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
644 }
645
646 /**
647 * @brief Set UCPD SNK role
648 * @rmtoll CR ANAMODE LL_UCPD_SetSNKRole
649 * @param UCPDx UCPD Instance
650 * @retval None
651 */
LL_UCPD_SetSNKRole(UCPD_TypeDef * UCPDx)652 __STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
653 {
654 SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
655 }
656
657 /**
658 * @brief Set UCPD SRC role
659 * @rmtoll CR ANAMODE LL_UCPD_SetSRCRole
660 * @param UCPDx UCPD Instance
661 * @retval None
662 */
LL_UCPD_SetSRCRole(UCPD_TypeDef * UCPDx)663 __STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
664 {
665 CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
666 }
667
668 /**
669 * @brief Get UCPD Role
670 * @rmtoll CR ANAMODE LL_UCPD_GetRole
671 * @param UCPDx UCPD Instance
672 * @retval Returned value can be one of the following values:
673 * @arg @ref LL_UCPD_ROLE_SNK
674 * @arg @ref LL_UCPD_ROLE_SRC
675 */
LL_UCPD_GetRole(UCPD_TypeDef const * const UCPDx)676 __STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
677 {
678 return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
679 }
680
681 /**
682 * @brief Set Rp resistor
683 * @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor
684 * @param UCPDx UCPD Instance
685 * @param Resistor This parameter can be one of the following values:
686 * @arg @ref LL_UCPD_RESISTOR_DEFAULT
687 * @arg @ref LL_UCPD_RESISTOR_1_5A
688 * @arg @ref LL_UCPD_RESISTOR_3_0A
689 * @arg @ref LL_UCPD_RESISTOR_NONE
690 * @retval None
691 */
LL_UCPD_SetRpResistor(UCPD_TypeDef * UCPDx,uint32_t Resistor)692 __STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
693 {
694 MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor);
695 }
696
697 /**
698 * @brief Set CC pin
699 * @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin
700 * @param UCPDx UCPD Instance
701 * @param CCPin This parameter can be one of the following values:
702 * @arg @ref LL_UCPD_CCPIN_CC1
703 * @arg @ref LL_UCPD_CCPIN_CC2
704 * @retval None
705 */
LL_UCPD_SetCCPin(UCPD_TypeDef * UCPDx,uint32_t CCPin)706 __STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
707 {
708 MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin);
709 }
710
711 /**
712 * @brief Rx enable
713 * @rmtoll CR PHYRXEN LL_UCPD_RxEnable
714 * @param UCPDx UCPD Instance
715 * @retval None
716 */
LL_UCPD_RxEnable(UCPD_TypeDef * UCPDx)717 __STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
718 {
719 SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
720 }
721
722 /**
723 * @brief Rx disable
724 * @rmtoll CR PHYRXEN LL_UCPD_RxDisable
725 * @param UCPDx UCPD Instance
726 * @retval None
727 */
LL_UCPD_RxDisable(UCPD_TypeDef * UCPDx)728 __STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
729 {
730 CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
731 }
732
733 /**
734 * @brief Set Rx mode
735 * @rmtoll CR RXMODE LL_UCPD_SetRxMode
736 * @param UCPDx UCPD Instance
737 * @param RxMode This parameter can be one of the following values:
738 * @arg @ref LL_UCPD_RXMODE_NORMAL
739 * @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
740 * @retval None
741 */
LL_UCPD_SetRxMode(UCPD_TypeDef * UCPDx,uint32_t RxMode)742 __STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
743 {
744 MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
745 }
746
747 /**
748 * @brief Send Hard Reset
749 * @rmtoll CR TXHRST LL_UCPD_SendHardReset
750 * @param UCPDx UCPD Instance
751 * @retval None
752 */
LL_UCPD_SendHardReset(UCPD_TypeDef * UCPDx)753 __STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
754 {
755 SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
756 }
757
758 /**
759 * @brief Send message
760 * @rmtoll CR TXSEND LL_UCPD_SendMessage
761 * @param UCPDx UCPD Instance
762 * @retval None
763 */
LL_UCPD_SendMessage(UCPD_TypeDef * UCPDx)764 __STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
765 {
766 SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
767 }
768
769 /**
770 * @brief Set Tx mode
771 * @rmtoll CR TXMODE LL_UCPD_SetTxMode
772 * @param UCPDx UCPD Instance
773 * @param TxMode This parameter can be one of the following values:
774 * @arg @ref LL_UCPD_TXMODE_NORMAL
775 * @arg @ref LL_UCPD_TXMODE_CABLE_RESET
776 * @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
777 * @retval None
778 */
LL_UCPD_SetTxMode(UCPD_TypeDef * UCPDx,uint32_t TxMode)779 __STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
780 {
781 MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
782 }
783
784 /**
785 * @}
786 */
787
788 /** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
789 * @{
790 */
791
792 /**
793 * @brief Enable type c event on CC2
794 * @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
795 * @param UCPDx UCPD Instance
796 * @retval None
797 */
LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef * UCPDx)798 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
799 {
800 SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
801 }
802
803 /**
804 * @brief Enable type c event on CC1
805 * @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
806 * @param UCPDx UCPD Instance
807 * @retval None
808 */
LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef * UCPDx)809 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
810 {
811 SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
812 }
813
814 /**
815 * @brief Enable Rx message end interrupt
816 * @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
817 * @param UCPDx UCPD Instance
818 * @retval None
819 */
LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef * UCPDx)820 __STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
821 {
822 SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
823 }
824
825 /**
826 * @brief Enable Rx overrun interrupt
827 * @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
828 * @param UCPDx UCPD Instance
829 * @retval None
830 */
LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef * UCPDx)831 __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
832 {
833 SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
834 }
835
836 /**
837 * @brief Enable Rx hard reset interrupt
838 * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
839 * @param UCPDx UCPD Instance
840 * @retval None
841 */
LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef * UCPDx)842 __STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
843 {
844 SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
845 }
846
847 /**
848 * @brief Enable Rx orderset interrupt
849 * @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
850 * @param UCPDx UCPD Instance
851 * @retval None
852 */
LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef * UCPDx)853 __STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
854 {
855 SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
856 }
857
858 /**
859 * @brief Enable Rx non empty interrupt
860 * @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE
861 * @param UCPDx UCPD Instance
862 * @retval None
863 */
LL_UCPD_EnableIT_RxNE(UCPD_TypeDef * UCPDx)864 __STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
865 {
866 SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
867 }
868
869 /**
870 * @brief Enable TX underrun interrupt
871 * @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND
872 * @param UCPDx UCPD Instance
873 * @retval None
874 */
LL_UCPD_EnableIT_TxUND(UCPD_TypeDef * UCPDx)875 __STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
876 {
877 SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
878 }
879
880 /**
881 * @brief Enable hard reset sent interrupt
882 * @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
883 * @param UCPDx UCPD Instance
884 * @retval None
885 */
LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef * UCPDx)886 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
887 {
888 SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
889 }
890
891 /**
892 * @brief Enable hard reset discard interrupt
893 * @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
894 * @param UCPDx UCPD Instance
895 * @retval None
896 */
LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef * UCPDx)897 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
898 {
899 SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
900 }
901
902 /**
903 * @brief Enable Tx message abort interrupt
904 * @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
905 * @param UCPDx UCPD Instance
906 * @retval None
907 */
LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef * UCPDx)908 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
909 {
910 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
911 }
912
913 /**
914 * @brief Enable Tx message sent interrupt
915 * @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
916 * @param UCPDx UCPD Instance
917 * @retval None
918 */
LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef * UCPDx)919 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
920 {
921 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
922 }
923
924 /**
925 * @brief Enable Tx message discarded interrupt
926 * @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
927 * @param UCPDx UCPD Instance
928 * @retval None
929 */
LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef * UCPDx)930 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
931 {
932 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
933 }
934
935 /**
936 * @brief Enable Tx data receive interrupt
937 * @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS
938 * @param UCPDx UCPD Instance
939 * @retval None
940 */
LL_UCPD_EnableIT_TxIS(UCPD_TypeDef * UCPDx)941 __STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
942 {
943 SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
944 }
945
946 /**
947 * @brief Disable type c event on CC2
948 * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
949 * @param UCPDx UCPD Instance
950 * @retval None
951 */
LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef * UCPDx)952 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
953 {
954 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
955 }
956
957 /**
958 * @brief Disable type c event on CC1
959 * @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
960 * @param UCPDx UCPD Instance
961 * @retval None
962 */
LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef * UCPDx)963 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
964 {
965 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
966 }
967
968 /**
969 * @brief Disable Rx message end interrupt
970 * @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
971 * @param UCPDx UCPD Instance
972 * @retval None
973 */
LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef * UCPDx)974 __STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
975 {
976 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
977 }
978
979 /**
980 * @brief Disable Rx overrun interrupt
981 * @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
982 * @param UCPDx UCPD Instance
983 * @retval None
984 */
LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef * UCPDx)985 __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
986 {
987 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
988 }
989
990 /**
991 * @brief Disable Rx hard reset interrupt
992 * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
993 * @param UCPDx UCPD Instance
994 * @retval None
995 */
LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef * UCPDx)996 __STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
997 {
998 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
999 }
1000
1001 /**
1002 * @brief Disable Rx orderset interrupt
1003 * @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
1004 * @param UCPDx UCPD Instance
1005 * @retval None
1006 */
LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef * UCPDx)1007 __STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
1008 {
1009 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
1010 }
1011
1012 /**
1013 * @brief Disable Rx non empty interrupt
1014 * @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE
1015 * @param UCPDx UCPD Instance
1016 * @retval None
1017 */
LL_UCPD_DisableIT_RxNE(UCPD_TypeDef * UCPDx)1018 __STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
1019 {
1020 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
1021 }
1022
1023 /**
1024 * @brief Disable TX underrun interrupt
1025 * @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND
1026 * @param UCPDx UCPD Instance
1027 * @retval None
1028 */
LL_UCPD_DisableIT_TxUND(UCPD_TypeDef * UCPDx)1029 __STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
1030 {
1031 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
1032 }
1033
1034 /**
1035 * @brief Disable hard reset sent interrupt
1036 * @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
1037 * @param UCPDx UCPD Instance
1038 * @retval None
1039 */
LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef * UCPDx)1040 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
1041 {
1042 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
1043 }
1044
1045 /**
1046 * @brief Disable hard reset discard interrupt
1047 * @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
1048 * @param UCPDx UCPD Instance
1049 * @retval None
1050 */
LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef * UCPDx)1051 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
1052 {
1053 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
1054 }
1055
1056 /**
1057 * @brief Disable Tx message abort interrupt
1058 * @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
1059 * @param UCPDx UCPD Instance
1060 * @retval None
1061 */
LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef * UCPDx)1062 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
1063 {
1064 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
1065 }
1066
1067 /**
1068 * @brief Disable Tx message sent interrupt
1069 * @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
1070 * @param UCPDx UCPD Instance
1071 * @retval None
1072 */
LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef * UCPDx)1073 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
1074 {
1075 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
1076 }
1077
1078 /**
1079 * @brief Disable Tx message discarded interrupt
1080 * @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
1081 * @param UCPDx UCPD Instance
1082 * @retval None
1083 */
LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef * UCPDx)1084 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
1085 {
1086 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
1087 }
1088
1089 /**
1090 * @brief Disable Tx data receive interrupt
1091 * @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS
1092 * @param UCPDx UCPD Instance
1093 * @retval None
1094 */
LL_UCPD_DisableIT_TxIS(UCPD_TypeDef * UCPDx)1095 __STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
1096 {
1097 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
1098 }
1099
1100 /**
1101 * @brief Check if type c event on CC2 enabled
1102 * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
1103 * @param UCPDx UCPD Instance
1104 * @retval State of bit (1 or 0).
1105 */
LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const * const UCPDx)1106 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
1107 {
1108 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
1109 }
1110
1111 /**
1112 * @brief Check if type c event on CC1 enabled
1113 * @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
1114 * @param UCPDx UCPD Instance
1115 * @retval State of bit (1 or 0).
1116 */
LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const * const UCPDx)1117 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
1118 {
1119 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
1120 }
1121
1122 /**
1123 * @brief Check if Rx message end interrupt enabled
1124 * @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
1125 * @param UCPDx UCPD Instance
1126 * @retval State of bit (1 or 0).
1127 */
LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const * const UCPDx)1128 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
1129 {
1130 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
1131 }
1132
1133 /**
1134 * @brief Check if Rx overrun interrupt enabled
1135 * @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
1136 * @param UCPDx UCPD Instance
1137 * @retval State of bit (1 or 0).
1138 */
LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const * const UCPDx)1139 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
1140 {
1141 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
1142 }
1143
1144 /**
1145 * @brief Check if Rx hard reset interrupt enabled
1146 * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
1147 * @param UCPDx UCPD Instance
1148 * @retval State of bit (1 or 0).
1149 */
LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const * const UCPDx)1150 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
1151 {
1152 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
1153 }
1154
1155 /**
1156 * @brief Check if Rx orderset interrupt enabled
1157 * @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
1158 * @param UCPDx UCPD Instance
1159 * @retval State of bit (1 or 0).
1160 */
LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const * const UCPDx)1161 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
1162 {
1163 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
1164 }
1165
1166 /**
1167 * @brief Check if Rx non empty interrupt enabled
1168 * @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
1169 * @param UCPDx UCPD Instance
1170 * @retval State of bit (1 or 0).
1171 */
LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const * const UCPDx)1172 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
1173 {
1174 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
1175 }
1176
1177 /**
1178 * @brief Check if TX underrun interrupt enabled
1179 * @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
1180 * @param UCPDx UCPD Instance
1181 * @retval State of bit (1 or 0).
1182 */
LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const * const UCPDx)1183 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
1184 {
1185 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
1186 }
1187
1188 /**
1189 * @brief Check if hard reset sent interrupt enabled
1190 * @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
1191 * @param UCPDx UCPD Instance
1192 * @retval State of bit (1 or 0).
1193 */
LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const * const UCPDx)1194 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
1195 {
1196 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
1197 }
1198
1199 /**
1200 * @brief Check if hard reset discard interrupt enabled
1201 * @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
1202 * @param UCPDx UCPD Instance
1203 * @retval State of bit (1 or 0).
1204 */
LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const * const UCPDx)1205 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
1206 {
1207 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
1208 }
1209
1210 /**
1211 * @brief Check if Tx message abort interrupt enabled
1212 * @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
1213 * @param UCPDx UCPD Instance
1214 * @retval State of bit (1 or 0).
1215 */
LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const * const UCPDx)1216 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
1217 {
1218 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
1219 }
1220
1221 /**
1222 * @brief Check if Tx message sent interrupt enabled
1223 * @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
1224 * @param UCPDx UCPD Instance
1225 * @retval State of bit (1 or 0).
1226 */
LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const * const UCPDx)1227 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
1228 {
1229 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
1230 }
1231
1232 /**
1233 * @brief Check if Tx message discarded interrupt enabled
1234 * @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
1235 * @param UCPDx UCPD Instance
1236 * @retval State of bit (1 or 0).
1237 */
LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const * const UCPDx)1238 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
1239 {
1240 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
1241 }
1242
1243 /**
1244 * @brief Check if Tx data receive interrupt enabled
1245 * @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS
1246 * @param UCPDx UCPD Instance
1247 * @retval State of bit (1 or 0).
1248 */
LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const * const UCPDx)1249 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
1250 {
1251 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
1252 }
1253
1254 /**
1255 * @}
1256 */
1257
1258 /** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
1259 * @{
1260 */
1261
1262 /**
1263 * @brief Clear type c event on CC2
1264 * @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
1265 * @param UCPDx UCPD Instance
1266 * @retval None
1267 */
LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef * UCPDx)1268 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
1269 {
1270 SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
1271 }
1272
1273 /**
1274 * @brief Clear type c event on CC1
1275 * @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
1276 * @param UCPDx UCPD Instance
1277 * @retval None
1278 */
LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef * UCPDx)1279 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
1280 {
1281 SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
1282 }
1283
1284 /**
1285 * @brief Clear Rx message end interrupt
1286 * @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
1287 * @param UCPDx UCPD Instance
1288 * @retval None
1289 */
LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef * UCPDx)1290 __STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
1291 {
1292 SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
1293 }
1294
1295 /**
1296 * @brief Clear Rx overrun interrupt
1297 * @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
1298 * @param UCPDx UCPD Instance
1299 * @retval None
1300 */
LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef * UCPDx)1301 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
1302 {
1303 SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
1304 }
1305
1306 /**
1307 * @brief Clear Rx hard reset interrupt
1308 * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
1309 * @param UCPDx UCPD Instance
1310 * @retval None
1311 */
LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef * UCPDx)1312 __STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
1313 {
1314 SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
1315 }
1316
1317 /**
1318 * @brief Clear Rx orderset interrupt
1319 * @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
1320 * @param UCPDx UCPD Instance
1321 * @retval None
1322 */
LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef * UCPDx)1323 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
1324 {
1325 SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
1326 }
1327
1328 /**
1329 * @brief Clear TX underrun interrupt
1330 * @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
1331 * @param UCPDx UCPD Instance
1332 * @retval None
1333 */
LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef * UCPDx)1334 __STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
1335 {
1336 SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
1337 }
1338
1339 /**
1340 * @brief Clear hard reset sent interrupt
1341 * @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
1342 * @param UCPDx UCPD Instance
1343 * @retval None
1344 */
LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef * UCPDx)1345 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
1346 {
1347 SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
1348 }
1349
1350 /**
1351 * @brief Clear hard reset discard interrupt
1352 * @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
1353 * @param UCPDx UCPD Instance
1354 * @retval None
1355 */
LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef * UCPDx)1356 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
1357 {
1358 SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
1359 }
1360
1361 /**
1362 * @brief Clear Tx message abort interrupt
1363 * @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
1364 * @param UCPDx UCPD Instance
1365 * @retval None
1366 */
LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef * UCPDx)1367 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
1368 {
1369 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
1370 }
1371
1372 /**
1373 * @brief Clear Tx message sent interrupt
1374 * @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
1375 * @param UCPDx UCPD Instance
1376 * @retval None
1377 */
LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef * UCPDx)1378 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
1379 {
1380 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
1381 }
1382
1383 /**
1384 * @brief Clear Tx message discarded interrupt
1385 * @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
1386 * @param UCPDx UCPD Instance
1387 * @retval None
1388 */
LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef * UCPDx)1389 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
1390 {
1391 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
1392 }
1393
1394 /**
1395 * @}
1396 */
1397
1398 /** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
1399 * @{
1400 */
1401
1402 /**
1403 * @brief Check if type c event on CC2
1404 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
1405 * @param UCPDx UCPD Instance
1406 * @retval State of bit (1 or 0).
1407 */
LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * const UCPDx)1408 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
1409 {
1410 return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
1411 }
1412
1413 /**
1414 * @brief Check if type c event on CC1
1415 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
1416 * @param UCPDx UCPD Instance
1417 * @retval State of bit (1 or 0).
1418 */
LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * const UCPDx)1419 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
1420 {
1421 return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
1422 }
1423
1424 /**
1425 * @brief Check if Rx error flag is active
1426 * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr
1427 * @param UCPDx UCPD Instance
1428 * @retval State of bit (1 or 0).
1429 */
LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const * const UCPDx)1430 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx)
1431 {
1432 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL);
1433 }
1434
1435 /**
1436 * @brief Check if Rx message end flag is active
1437 * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
1438 * @param UCPDx UCPD Instance
1439 * @retval State of bit (1 or 0).
1440 */
LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const * const UCPDx)1441 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
1442 {
1443 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
1444 }
1445
1446 /**
1447 * @brief Check if Rx overrun flag is active
1448 * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
1449 * @param UCPDx UCPD Instance
1450 * @retval State of bit (1 or 0).
1451 */
LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const * const UCPDx)1452 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
1453 {
1454 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
1455 }
1456
1457 /**
1458 * @brief Check if Rx hard reset flag is active
1459 * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
1460 * @param UCPDx UCPD Instance
1461 * @retval State of bit (1 or 0).
1462 */
LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const * const UCPDx)1463 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
1464 {
1465 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
1466 }
1467
1468 /**
1469 * @brief Check if Rx orderset flag is active
1470 * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
1471 * @param UCPDx UCPD Instance
1472 * @retval State of bit (1 or 0).
1473 */
LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const * const UCPDx)1474 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
1475 {
1476 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
1477 }
1478
1479 /**
1480 * @brief Check if Rx non empty flag is active
1481 * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE
1482 * @param UCPDx UCPD Instance
1483 * @retval State of bit (1 or 0).
1484 */
LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const * const UCPDx)1485 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
1486 {
1487 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
1488 }
1489
1490 /**
1491 * @brief Check if TX underrun flag is active
1492 * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND
1493 * @param UCPDx UCPD Instance
1494 * @retval State of bit (1 or 0).
1495 */
LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const * const UCPDx)1496 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
1497 {
1498 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
1499 }
1500
1501 /**
1502 * @brief Check if hard reset sent flag is active
1503 * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
1504 * @param UCPDx UCPD Instance
1505 * @retval State of bit (1 or 0).
1506 */
LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const * const UCPDx)1507 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
1508 {
1509 return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
1510 }
1511
1512 /**
1513 * @brief Check if hard reset discard flag is active
1514 * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
1515 * @param UCPDx UCPD Instance
1516 * @retval State of bit (1 or 0).
1517 */
LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const * const UCPDx)1518 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
1519 {
1520 return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
1521 }
1522
1523 /**
1524 * @brief Check if Tx message abort flag is active
1525 * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
1526 * @param UCPDx UCPD Instance
1527 * @retval State of bit (1 or 0).
1528 */
LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const * const UCPDx)1529 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
1530 {
1531 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
1532 }
1533
1534 /**
1535 * @brief Check if Tx message sent flag is active
1536 * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
1537 * @param UCPDx UCPD Instance
1538 * @retval State of bit (1 or 0).
1539 */
LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const * const UCPDx)1540 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
1541 {
1542 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
1543 }
1544
1545 /**
1546 * @brief Check if Tx message discarded flag is active
1547 * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
1548 * @param UCPDx UCPD Instance
1549 * @retval State of bit (1 or 0).
1550 */
LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const * const UCPDx)1551 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
1552 {
1553 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
1554 }
1555
1556 /**
1557 * @brief Check if Tx data interrupt flag is active
1558 * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS
1559 * @param UCPDx UCPD Instance
1560 * @retval State of bit (1 or 0).
1561 */
LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const * const UCPDx)1562 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
1563 {
1564 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
1565 }
1566
1567 /**
1568 * @brief return the vstate value for CC2
1569 * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2
1570 * @param UCPDx UCPD Instance
1571 * @retval val
1572 */
LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const * const UCPDx)1573 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
1574 {
1575 return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
1576 }
1577
1578 /**
1579 * @brief return the vstate value for CC1
1580 * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1
1581 * @param UCPDx UCPD Instance
1582 * @retval val
1583 */
LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const * const UCPDx)1584 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
1585 {
1586 return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
1587 }
1588
1589 /**
1590 * @}
1591 */
1592
1593
1594 /** @defgroup UCPD_LL_EF_DMA_Management DMA Management
1595 * @{
1596 */
1597
1598 /**
1599 * @brief Rx DMA Enable
1600 * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable
1601 * @param UCPDx UCPD Instance
1602 * @retval None
1603 */
LL_UCPD_RxDMAEnable(UCPD_TypeDef * UCPDx)1604 __STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
1605 {
1606 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
1607 }
1608
1609 /**
1610 * @brief Rx DMA Disable
1611 * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable
1612 * @param UCPDx UCPD Instance
1613 * @retval None
1614 */
LL_UCPD_RxDMADisable(UCPD_TypeDef * UCPDx)1615 __STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
1616 {
1617 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
1618 }
1619
1620 /**
1621 * @brief Tx DMA Enable
1622 * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable
1623 * @param UCPDx UCPD Instance
1624 * @retval None
1625 */
LL_UCPD_TxDMAEnable(UCPD_TypeDef * UCPDx)1626 __STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
1627 {
1628 SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
1629 }
1630
1631 /**
1632 * @brief Tx DMA Disable
1633 * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable
1634 * @param UCPDx UCPD Instance
1635 * @retval None
1636 */
LL_UCPD_TxDMADisable(UCPD_TypeDef * UCPDx)1637 __STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
1638 {
1639 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
1640 }
1641
1642 /**
1643 * @brief Check if DMA Tx is enabled
1644 * @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
1645 * @param UCPDx UCPD Instance
1646 * @retval State of bit (1 or 0).
1647 */
LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const * const UCPDx)1648 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
1649 {
1650 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
1651 }
1652
1653 /**
1654 * @brief Check if DMA Rx is enabled
1655 * @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
1656 * @param UCPDx UCPD Instance
1657 * @retval State of bit (1 or 0).
1658 */
LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const * const UCPDx)1659 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
1660 {
1661 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
1662 }
1663
1664 /**
1665 * @}
1666 */
1667
1668 /** @defgroup UCPD_LL_EF_DATA_Management DATA Management
1669 * @{
1670 */
1671
1672 /**
1673 * @brief write the orderset for Tx message
1674 * @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
1675 * @param UCPDx UCPD Instance
1676 * @param TxOrderSet one of the following value
1677 * @arg @ref LL_UCPD_ORDERED_SET_SOP
1678 * @arg @ref LL_UCPD_ORDERED_SET_SOP1
1679 * @arg @ref LL_UCPD_ORDERED_SET_SOP2
1680 * @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
1681 * @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
1682 * @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
1683 * @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
1684 * @retval None
1685 */
LL_UCPD_WriteTxOrderSet(UCPD_TypeDef * UCPDx,uint32_t TxOrderSet)1686 __STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
1687 {
1688 WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
1689 }
1690
1691 /**
1692 * @brief write the Tx paysize
1693 * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
1694 * @param UCPDx UCPD Instance
1695 * @param TxPaySize
1696 * @retval None.
1697 */
LL_UCPD_WriteTxPaySize(UCPD_TypeDef * UCPDx,uint32_t TxPaySize)1698 __STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
1699 {
1700 WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
1701 }
1702
1703 /**
1704 * @brief Write data
1705 * @rmtoll TXDR DR LL_UCPD_WriteData
1706 * @param UCPDx UCPD Instance
1707 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1708 * @retval None.
1709 */
LL_UCPD_WriteData(UCPD_TypeDef * UCPDx,uint8_t Data)1710 __STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
1711 {
1712 WRITE_REG(UCPDx->TXDR, Data);
1713 }
1714
1715 /**
1716 * @brief read RX the orderset
1717 * @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
1718 * @param UCPDx UCPD Instance
1719 * @retval RxOrderSet one of the following value
1720 * @arg @ref LL_UCPD_RXORDSET_SOP
1721 * @arg @ref LL_UCPD_RXORDSET_SOP1
1722 * @arg @ref LL_UCPD_RXORDSET_SOP2
1723 * @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
1724 * @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
1725 * @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
1726 * @arg @ref LL_UCPD_RXORDSET_SOPEXT1
1727 * @arg @ref LL_UCPD_RXORDSET_SOPEXT2
1728 */
LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const * const UCPDx)1729 __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
1730 {
1731 return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
1732 }
1733
1734 /**
1735 * @brief Read the Rx paysize
1736 * @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize
1737 * @param UCPDx UCPD Instance
1738 * @retval RXPaysize.
1739 */
LL_UCPD_ReadRxPaySize(UCPD_TypeDef const * const UCPDx)1740 __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
1741 {
1742 return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
1743 }
1744
1745 /**
1746 * @brief Read data
1747 * @rmtoll RXDR RXDATA LL_UCPD_ReadData
1748 * @param UCPDx UCPD Instance
1749 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1750 */
LL_UCPD_ReadData(UCPD_TypeDef const * const UCPDx)1751 __STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
1752 {
1753 return READ_REG(UCPDx->RXDR);
1754 }
1755
1756 /**
1757 * @brief Set Rx OrderSet Ext1
1758 * @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
1759 * @param UCPDx UCPD Instance
1760 * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
1761 * @retval None
1762 */
LL_UCPD_SetRxOrdExt1(UCPD_TypeDef * UCPDx,uint32_t SOPExt)1763 __STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
1764 {
1765 WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
1766 }
1767
1768 /**
1769 * @brief Set Rx OrderSet Ext2
1770 * @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
1771 * @param UCPDx UCPD Instance
1772 * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
1773 * @retval None
1774 */
LL_UCPD_SetRxOrdExt2(UCPD_TypeDef * UCPDx,uint32_t SOPExt)1775 __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
1776 {
1777 WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
1778 }
1779
1780 /**
1781 * @}
1782 */
1783
1784 #if defined(USE_FULL_LL_DRIVER)
1785 /** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
1786 * @{
1787 */
1788
1789 ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
1790 ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct);
1791 void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
1792
1793 /**
1794 * @}
1795 */
1796 #endif /* USE_FULL_LL_DRIVER */
1797
1798 /**
1799 * @}
1800 */
1801
1802 #endif /* defined (UCPD1) */
1803
1804 /**
1805 * @}
1806 */
1807
1808 /**
1809 * @}
1810 */
1811
1812 #ifdef __cplusplus
1813 }
1814 #endif
1815
1816 #endif /* STM32N6xx_LL_UCPD_H */
1817
1818
