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Searched +full:sysclk +full:- +full:prescaler (Results 1 – 25 of 29) sorted by relevance

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/Zephyr-latest/dts/bindings/clock/
Dst,stm32h7-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This node is in charge of system clock ('SYSCLK') source selection and
13 As part of this node configuration, SYSCLK frequency should also be defined, using
14 "clock-frequency" property.
16 prescaler properties.
19 clocks = <&pll>; /* Set pll as SYSCLK source */
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
33 include: [clock-controller.yaml, base.yaml]
[all …]
Dst,stm32h7rs-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This node is in charge of system clock ('SYSCLK') source selection and
13 As part of this node configuration, SYSCLK frequency should also be defined, using
14 "clock-frequency" property.
16 prescaler properties.
19 clocks = <&pll>; /* Set pll as SYSCLK source */
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7rs-rcc"
33 include: [clock-controller.yaml, base.yaml]
[all …]
Dadi,max32-gcr.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-gcr"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 sysclk-prescaler:
20 - 1
21 - 2
22 - 4
23 - 8
[all …]
Dst,stm32wb0-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This node is in charge of the system clock ('SYSCLK') source
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
26 slow-clock:
35 clksys-prescaler:
39 - 1
40 - 2
[all …]
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 matching prescaler properties.
20 clocks = <&pll>; /* Select pll as SYSCLK source */
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
[all …]
Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 prescaler properties.
20 clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-prescaler = <1>;
24 apb2-prescaler = <1>;
[all …]
Dst,stm32wb-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 For more description confere st,stm32-rcc.yaml
8 compatible: "st,stm32wb-rcc"
11 - name: st,stm32-rcc.yaml
12 property-blocklist:
13 - ahb-prescaler
16 cpu1-prescaler:
20 - 1
21 - 2
22 - 3
[all …]
Dst,stm32f100-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
8 When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
9 pll2, configurable prescaler is used.
14 f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
23 compatible: "st,stm32f100-pll-clock"
26 - name: st,stm32f105-pll-clock.yaml
27 property-blocklist:
28 - mul
36 Valid range: 2 - 16
Dst,stm32f105-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
8 When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
9 pll2, configurable prescaler is used.
13 f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
22 compatible: "st,stm32f105-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
40 - 4 # x4
41 - 5 # x5
42 - 6 # x6
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h7.c7 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
78 /* SYSCLKSRC before the D1CPRE prescaler */
89 /* ARM Sys CPU Clock before HPRE prescaler */
113 /* All h7 SoC with maximum 480MHz SYSCLK */
121 /* All h7 SoC with maximum 550MHz SYSCLK */
132 /* All h7RS SoC with maximum 500MHz SYSCLK (refer to Datasheet DS14359 rev 1) */
137 /* Default: All h7 SoC with maximum 280MHz SYSCLK */
144 #error "SYSCLK frequency is too high!"
169 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
[all …]
Dclock_stm32_ll_wb0.c4 * SPDX-License-Identifier: Apache-2.0
43 # error slow-clock source is not enabled
53 # error Invalid device selected as slow-clock
66 "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE");
108 * NOTE: (size - 1) is required to get the correct count, in measure_lsi_frequency()
113 (CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW - 1)); in measure_lsi_frequency()
137 * LSI calibration counts the amount of 16MHz clock half-periods that in measure_lsi_frequency()
140 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods in measure_lsi_frequency()
155 * = ------------------------------------------------ in measure_lsi_frequency()
163 * = ------------------------------------------------ in measure_lsi_frequency()
[all …]
Dclock_stm32_ll_wba.c4 * SPDX-License-Identifier: Apache-2.0
19 /* Macros to fill up prescaler values */
38 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
40 return clock / prescaler; in get_bus_clock()
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
[all …]
Dclock_stm32_ll_u5.c6 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
39 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
41 return clock / prescaler; in get_bus_clock()
117 __ASSERT(0, "No SYSCLK Source configured"); in get_sysclk_frequency()
150 return -ENOTSUP; in enabled_clock()
161 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
163 return -ENOTSUP; in stm32_clock_control_on()
166 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
167 pclken->enr); in stm32_clock_control_on()
[all …]
Dclock_stm32_ll_common.c2 * Copyright (c) 2017-2022 Linaro Limited.
5 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
76 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
81 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
100 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
102 return clock / prescaler; in get_bus_clock()
136 r = -ENOTSUP; in enabled_clock()
150 r = -ENOTSUP; in enabled_clock()
157 r = -ENOTSUP; in enabled_clock()
[all …]
Dclock_stm32_ll_h5.c7 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
42 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
44 return clock / prescaler; in get_bus_clock()
112 __ASSERT(0, "No SYSCLK Source configured"); in get_sysclk_frequency()
144 return -ENOTSUP; in enabled_clock()
155 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
157 return -ENOTSUP; in stm32_clock_control_on()
160 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
161 pclken->enr); in stm32_clock_control_on()
[all …]
/Zephyr-latest/boards/google/dragonclaw/
Dgoogle_dragonclaw.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <st/f4/stm32f412c(e-g)ux-pinctrl.dtsi>
14 compatible = "google,dragonclaw-fpmcu";
18 zephyr,shell-uart = &usart2;
21 zephyr,flash-controller = &flash;
36 div-m = <8>;
37 mul-n = <192>; /* 16MHz * 192/8 = 384MHz VCO clock */
38 div-p = <4>; /* 96MHz PLL general clock output */
39 div-q = <8>; /* 48MHz PLL output for USB, SDIO, RNG */
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
/Zephyr-latest/boards/st/nucleo_u5a5zj_q/
Dnucleo_u5a5zj_q-common.dtsi2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/u5/stm32u5a5zjtxq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "gpio-leds";
30 compatible = "gpio-keys";
39 compatible = "pwm-leds";
60 clock-frequency = <DT_FREQ_M(16)>;
69 /* HSE 16MHz source, outputting 160MHz to sysclk and apbclk */
70 div-m = <4>; /* input divisor */
[all …]
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4xxx.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/gpio/infineon-xmc4xxx-gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-m4f";
25 compatible = "infineon,xmc4xxx-flash-controller";
27 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32bg2x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/pinctrl/gecko-pinctrl.h>
11 #include <dt-bindings/adc/adc.h>
16 zephyr,flash-controller = &msc;
21 sysclk: sysclk { label
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
[all …]
Defr32mg21.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/clock/silabs/xg21-clock.h>
17 zephyr,flash-controller = &msc;
21 sysclk: sysclk { label
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
[all …]
Defr32mg24.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/adc/adc.h>
11 #include <dt-bindings/clock/silabs/xg24-clock.h>
16 zephyr,flash-controller = &msc;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
[all …]
Defr32xg23.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/adc/adc.h>
11 #include <dt-bindings/clock/silabs/xg23-clock.h>
16 zephyr,flash-controller = &msc;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
27 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/adi/max32/
Dmax32xxx.dtsi2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/adi_max32_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
18 zephyr,flash-controller = &flc0;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt1010.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 flexram,num-ram-banks = <4>;
12 flexram,bank-spec = <FLEXRAM_OCRAM>,
18 &sysclk {
19 clock-frequency = <500000000>;
35 /delete-node/ arm-podf;
37 ipg-podf {
38 clock-div = <4>;
61 irq-shared-offset = <0>;
62 dma-channels = <16>;
[all …]

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