1# Copyright (c) 2024 STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32WB0 Reset and Clock controller node for STM32WB0 devices
6  This node is in charge of the system clock ('SYSCLK') source
7  selection and generation.
8
9compatible: "st,stm32wb0-rcc"
10
11include: [clock-controller.yaml, base.yaml]
12
13properties:
14  reg:
15    required: true
16
17  "#clock-cells":
18    const: 2
19
20  clock-frequency:
21    required: true
22    type: int
23    description: |
24      default frequency in Hz for clock output
25
26  slow-clock:
27    type: phandle
28    description: |
29      Slow clock source selection.
30      On STM32WB0, all slow clock devices are clocked from the same
31      slow clock source, which is selected by this property.
32
33      The slow clock can be either clk_lsi, clk_lse, or clk_16mhz_div512.
34
35  clksys-prescaler:
36    type: int
37    required: true
38    enum:
39      - 1
40      - 2
41      - 4
42      - 8
43      - 16
44      - 32
45      - 64
46    description: |
47      CLK_SYS prescaler. Defines actual core clock frequency (CLK_SYS) based
48      on system frequency input (SYSCLK).
49      The CLK_SYS is used to clock the CPU, AHB, APB, memories and PKA.
50
51      NOTE: if the 32MHz HSE is used as SYSCLK source, the prescaler cannot
52      be set to 64.
53
54clock-cells:
55  - bus
56  - bits
57