Lines Matching +full:sysclk +full:- +full:prescaler

2 # SPDX-License-Identifier: Apache-2.0
6   This node is in charge of system clock ('SYSCLK') source selection and controlling
13   Core clock frequency should also be defined, using "clock-frequency" property.
15           Core clock frequency  = SYSCLK / AHB prescaler
17   prescaler properties.
20            clocks = <&pll>;  /* Select 80MHz pll as SYSCLK source */
21            ahb-prescaler = <2>;
22            clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23            apb1-prescaler = <1>;
24            apb2-prescaler = <1>;
81 compatible: "st,stm32-rcc"
83 include: [clock-controller.yaml, base.yaml]
89   "#clock-cells":
92   clock-frequency:
98   ahb-prescaler:
102       - 1
103       - 2
104       - 4
105       - 8
106       - 16
107       - 64
108       - 128
109       - 256
110       - 512
112         AHB prescaler. Defines actual core clock frequency (HCLK)
116   apb1-prescaler:
120       - 1
121       - 2
122       - 4
123       - 8
124       - 16
126   apb2-prescaler:
130       - 1
131       - 2
132       - 4
133       - 8
134       - 16
136   undershoot-prevention:
141       This is done by applying an intermediate AHB prescaler before switching
142       System Clock source to PLL. Once done, prescaler is set back to expected
145 clock-cells:
146   - bus
147   - bits