1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Reset and Clock controller node.
6  This node is in charge of system clock ('SYSCLK') source selection and controlling
7  clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
8
9  Configuring STM32 Reset and Clock controller node:
10
11  System clock source should be selected amongst the clock nodes available in "clocks"
12  node (typically 'clk_hse, clk_hsi', 'pll', ...).
13  Core clock frequency should also be defined, using "clock-frequency" property.
14  Note:
15          Core clock frequency  = SYSCLK / AHB prescaler
16  Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
17  prescaler properties.
18  Here is an example of correctly configured rcc node:
19  &rcc {
20           clocks = <&pll>;  /* Select 80MHz pll as SYSCLK source */
21           ahb-prescaler = <2>;
22           clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23           apb1-prescaler = <1>;
24           apb2-prescaler = <1>;
25  }
26
27  Specifying a gated clock:
28
29  To specify a gated clock, a peripheral should define a "clocks" property encoded
30  in the following way:
31  ... {
32           ...
33           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
34           ...
35  }
36  After the phandle referring to rcc node, the first index specifies the registers of
37  the bus controlling the peripheral and the second index specifies the bit used to
38  control the peripheral clock in that bus register.
39  The gated clock is required when accessing to the peripheral controller is needed
40  (generally for configuring the device). If dual clock domain is not used, it is
41  also used for peripheral operation.
42
43  Specifying a domain clock source:
44
45  Specifying a domain source clock could be done by adding a clock specifier to the
46  clock property:
47  ... {
48           ...
49           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
50                        <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
51           ...
52  }
53  In this example, I2C1 device is assigned HSI as domain clock source.
54  Domain clock is independent from the bus/gated clock and allows access to the device's
55  register while the gated clock is off. As it doesn't feed the peripheral's controller, it
56  allows peripheral operation, but can't be used for peripheral configuration.
57  It is peripheral driver's responsibility to query and use clock source information in
58  accordance with clock_control API specifications.
59
60  Since the peripheral subsystem rate is dictated by the clock used for peripheral
61  operation, same clock should be used in calls to `clock_control_get_rate()`
62
63  Note 1: No additional specifier means gating clock is also the clock source (ie
64          'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
65          cell to explicitly set it.
66  Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
67          should be the one matching SoC reset state. Confere reference manual to check
68          what is the reset value of the clock source for each peripheral.
69
70  Specifying a divided domain clock source:
71
72  Some peripherals are sourced through fixed clock dividers. For such cases there is
73  STM32_CLOCK_DIV() macro, which allows to specify such divider value. Selecting HSE/2 (HSE
74  frequency divided by 2) is done with following clock property:
75  ... {
76           ...
77           clocks = <&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
78           ...
79  }
80
81compatible: "st,stm32-rcc"
82
83include: [clock-controller.yaml, base.yaml]
84
85properties:
86  reg:
87    required: true
88
89  "#clock-cells":
90    const: 2
91
92  clock-frequency:
93    required: true
94    type: int
95    description: |
96      default frequency in Hz for clock output
97
98  ahb-prescaler:
99    type: int
100    required: true
101    enum:
102      - 1
103      - 2
104      - 4
105      - 8
106      - 16
107      - 64
108      - 128
109      - 256
110      - 512
111    description: |
112        AHB prescaler. Defines actual core clock frequency (HCLK)
113        based on system frequency input.
114        The HCLK clocks CPU, AHB, memories and DMA.
115
116  apb1-prescaler:
117    type: int
118    required: true
119    enum:
120      - 1
121      - 2
122      - 4
123      - 8
124      - 16
125
126  apb2-prescaler:
127    type: int
128    required: true
129    enum:
130      - 1
131      - 2
132      - 4
133      - 8
134      - 16
135
136  undershoot-prevention:
137    type: boolean
138    description: |
139      On some parts, it could be required to set up highest core frequencies
140      (>80MHz) in two steps in order to prevent undershoot.
141      This is done by applying an intermediate AHB prescaler before switching
142      System Clock source to PLL. Once done, prescaler is set back to expected
143      value.
144
145clock-cells:
146  - bus
147  - bits
148