1/*
2 * Copyright (c) 2022 Google LLC
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <st/f4/stm32f412Xg.dtsi>
10#include <st/f4/stm32f412c(e-g)ux-pinctrl.dtsi>
11
12/ {
13	model = "Google Dragonclaw development board";
14	compatible = "google,dragonclaw-fpmcu";
15
16	chosen {
17		zephyr,console = &usart2;
18		zephyr,shell-uart = &usart2;
19		zephyr,sram = &sram0;
20		zephyr,flash = &flash0;
21		zephyr,flash-controller = &flash;
22	};
23};
24
25&clk_hsi {
26	/* HSI clock frequency is 16MHz */
27	status = "okay";
28};
29
30&clk_lsi {
31	/* LSI clock frequency is 32768kHz */
32	status = "okay";
33};
34
35&pll {
36	div-m = <8>;
37	mul-n = <192>; /* 16MHz * 192/8 = 384MHz VCO clock */
38	div-p = <4>; /* 96MHz PLL general clock output */
39	div-q = <8>; /* 48MHz PLL output for USB, SDIO, RNG */
40	div-r = <7>; /* I2S - lowest possible frequency to save power */
41	clocks = <&clk_hsi>;
42	status = "okay";
43};
44
45&rcc {
46	clocks = <&pll>; /* Select PLL as SYSCLK source (96MHz) */
47	ahb-prescaler = <1>; /* SYSCLK not divided */
48	clock-frequency = <DT_FREQ_M(96)>; /* AHB frequency */
49	apb1-prescaler = <2>; /* AHB clock divided by 2 */
50	apb2-prescaler = <2>; /* AHB clock divided by 2 */
51};
52
53/* USART1: AP UART (Host Commands and MKBP) */
54&usart1 {
55	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
56	pinctrl-names = "default";
57	current-speed = <115200>;
58	status = "okay";
59};
60
61/* USART2: Servo UART (console) */
62&usart2 {
63	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
64	pinctrl-names = "default";
65	current-speed = <115200>;
66	status = "okay";
67};
68
69/* SPI1: communication with the AP */
70&spi1 {
71	pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
72		     &spi1_miso_pa6 &spi1_mosi_pa7>;
73	pinctrl-names = "default";
74	status = "okay";
75};
76
77/* SPI2: communication with the fingerprint sensor */
78&spi2 {
79	pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
80		     &spi2_miso_pb14 &spi2_mosi_pb15>;
81	pinctrl-names = "default";
82	status = "okay";
83};
84
85&rtc {
86	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
87		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
88	status = "okay";
89
90	backup_regs {
91		status = "okay";
92	};
93};
94
95&rng {
96	status = "okay";
97};
98
99/*
100 * Set flags of unused pins as GPIO_ACTIVE_HIGH (0 << 0), which will be
101 * interpreted by GPIO driver as GPIO_DISCONNECTED, without setting the gpio as
102 * either input or output. The STM32 GPIO driver will set these pins as analog
103 * to reduce power consumption.
104 */
105&gpiob {
106	unused {
107		gpio-hog;
108		gpios = <2 GPIO_ACTIVE_HIGH>, <5 GPIO_ACTIVE_HIGH>;
109	};
110};
111
112&gpioc {
113	unused {
114		gpio-hog;
115		gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>,
116			<15 GPIO_ACTIVE_HIGH>;
117	};
118};
119
120&gpioh {
121	unused {
122		gpio-hog;
123		gpios = <0 GPIO_ACTIVE_HIGH>, <1 GPIO_ACTIVE_HIGH>;
124	};
125};
126
127/*
128 * The board uses STM32F412CG in UFQFPN48 package in which gpio[d-g] is not
129 * exposed, so disable it.
130 */
131&gpiod {status = "disabled";};
132&gpioe {status = "disabled";};
133&gpiof {status = "disabled";};
134&gpiog {status = "disabled";};
135