Lines Matching +full:sysclk +full:- +full:prescaler

2 # SPDX-License-Identifier: Apache-2.0
8   When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
9   pll2, configurable prescaler is used.
13     f(PLLCLK) = f(PLLIN) x PLLMUL         --> SYSCLK (System Clock)
22 compatible: "st,stm32f105-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
40       - 4   # x4
41       - 5   # x5
42       - 6   # x6
43       - 7   # x7
44       - 8   # x8
45       - 9   # x9
46       - 15  # x6.5
52         Configurable prescaler
53         Valid range: 1 - 16