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/Zephyr-latest/dts/arm/ene/
Dkb1200.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-m4";
24 clock-frequency = <DT_FREQ_M(48)>;
29 compatible = "mmio-sram";
34 flash-controller@50100000 {
35 compatible = "ene,kb1200-flash-controller";
37 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/st/f3/
Dstm32f373.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/stm32f1_adc.h>
12 compatible = "st,stm32f373", "st,stm32f3", "simple-bus";
19 compatible = "st,stm32f1-rcc";
22 pinctrl: pin-controller@48000000 {
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
33 compatible = "st,stm32-i2c-v2";
34 clock-frequency = <I2C_BITRATE_STANDARD>;
[all …]
Dstm32f303.dtsi2 * Copyright (c) 2017 I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
12 compatible = "st,stm32f303", "st,stm32f3", "simple-bus";
20 compatible = "st,stm32-i2c-v2";
21 clock-frequency = <I2C_BITRATE_STANDARD>;
22 #address-cells = <1>;
23 #size-cells = <0>;
31 interrupt-names = "event", "error";
36 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
[all …]
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e10x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(120)>;
[all …]
/Zephyr-latest/tests/drivers/build_all/pwm/boards/
Dnative_sim.overlay3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 clock-frequency = <100000>;
25 compatible = "maxim,max31790-pwm";
27 pwm-controller;
28 #pwm-cells = <2>;
34 compatible = "nxp,pca9685-pwm";
[all …]
/Zephyr-latest/dts/riscv/ite/
Dit8801-common-cfg.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <ite/it8801-mfd-map.dtsi>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 compatible = "ite,it8801-gpio";
21 gpio-controller;
22 #gpio-cells = <2>;
24 pin-mask = <0xdb>;
28 compatible = "ite,it8801-gpio";
34 gpio-controller;
[all …]
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e507xe.dtsi4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "gd,gd32-timer";
16 interrupt-names = "brk", "up", "trgcom", "cc";
19 is-advanced;
23 pwm {
24 compatible = "gd,gd32-pwm";
26 #pwm-cells = <3>;
31 compatible = "gd,gd32-timer";
34 interrupt-names = "global";
40 pwm {
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/clock/npcx_clock.h>
12 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
16 #include <zephyr/dt-bindings/pwm/pwm.h>
17 #include <zephyr/dt-bindings/sensor/npcx_tach.h>
[all …]
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32f403.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f4xx.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dcyw20829.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m33";
19 cpu-power-states = <&idle &suspend_to_ram>;
22 power-states {
24 compatible = "zephyr,power-state";
25 power-state-name = "suspend-to-idle";
26 min-residency-us = <1000000>;
30 compatible = "zephyr,power-state";
[all …]
/Zephyr-latest/dts/arm/microchip/mec5/
Dmec5_pkg176_pwms.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* So far all Microchip MEC5 family of SoC's so add three more PWM's
8 * in the 176-pin (LJ) package.
11 pwm9: pwm@40005890 {
14 #pwm-cells = <3>;
16 pwm10: pwm@400058a0 {
19 #pwm-cells = <3>;
21 pwm11: pwm@400058b0 {
24 #pwm-cells = <3>;
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f4_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &sci2;
12 /delete-node/ &sci3;
13 /delete-node/ &ioport6;
14 /delete-node/ &ioport7;
15 /delete-node/ &ioport8;
20 compatible = "mmio-sram";
25 compatible = "renesas,ra-spi";
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt118x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/clock/imx_ccm_rev2.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
23 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xg.dtsi1 /* SPDX-License-Identifier: Apache-2.0
18 flash-controller@40022000 {
22 * This matters if you're doing in-application
24 * read-while-write capabilities, but is
25 * otherwise a non-issue.
28 erase-block-size = <DT_SIZE_K(2)>;
33 compatible = "st,stm32-timers";
42 pwm {
43 compatible = "st,stm32-pwm";
45 #pwm-cells = <3>;
[all …]
/Zephyr-latest/dts/arm/ti/
Dcc13xx_cc26xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
16 zephyr,flash-controller = &flash_controller;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-m4";
[all …]
/Zephyr-latest/dts/arm/st/f0/
Dstm32f0.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv6-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f0_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
[all …]
/Zephyr-latest/dts/bindings/test/
Dvnd,pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: VND PWM controller
6 compatible: "vnd,pwm"
8 include: [pwm-controller.yaml, base.yaml]
14 "#pwm-cells":
17 pwm-cells:
18 - channel
19 - period
20 - flags
/Zephyr-latest/dts/arm/st/c0/
Dstm32c0.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32c0_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/dma/stm32_dma.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dmicrochip,xec-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC PWM
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwm"
17 description: PWM PCR register index and bit position
19 "#pwm-cells":
22 pwm-cells:
23 - channel
24 - period
25 - flags
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dra6-cm4-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
10 #include <zephyr/dt-bindings/clock/ra_clock.h>
11 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
23 #address-cells = <1>;
24 #size-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/flash_controller/ospi.h>
10 #include <zephyr/dt-bindings/flash_controller/xspi.h>
17 #clock-cells = <0>;
18 compatible = "st,stm32u5-pll-clock";
24 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
26 pinctrl: pin-controller@42020000 {
28 compatible = "st,stm32-gpio";
29 gpio-controller;
30 #gpio-cells = <2>;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dpwm-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
5 An external clock signal driven by a PWM pin.
11 compatible = "pwm-clock";
12 #clock-cells = <1>;
16 This will create a device node with a clock-controller
17 API. Internally the device node will use PWM API to start the
21 The clock frequency can be explicitly set using the clock-frequency
24 The PWM node may need to be properly configured to generate
26 for the target PWM driver.
28 compatible: "pwm-clock"
[all …]

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