1/* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <dt-bindings/clock/imx_ccm_rev2.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/adc/adc.h> 11#include <zephyr/dt-bindings/pwm/pwm.h> 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-m33f"; 21 reg = <0>; 22 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 mpu: mpu@e000ed90 { 27 compatible = "arm,armv8m-mpu"; 28 reg = <0xe000ed90 0x40>; 29 }; 30 }; 31 cpu@1 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-m7"; 34 reg = <1>; 35 36 #address-cells = <1>; 37 #size-cells = <1>; 38 }; 39 }; 40}; 41 42&peripheral { 43 #address-cells = <1>; 44 #size-cells = <1>; 45 /* 46 * Note that the offsets here are relative to the base address 47 * defined in either nxp_rt118x_cm33_ns.dtsi, nxp_rt118x_cm33.dtsi 48 * or nxp_rt118x_cm7.dtsi. The base addresses on cm33 core differ 49 * between non-secure (0x40000000) and secure modes (0x50000000). 50 */ 51 iomuxc: iomuxc@2A10000 { 52 compatible = "nxp,imx-iomuxc"; 53 reg = <0x2A10000 0x4000>; 54 pinctrl: pinctrl { 55 status = "okay"; 56 compatible = "nxp,mcux-rt11xx-pinctrl"; 57 }; 58 }; 59 60 iomuxc_aon: iomuxc@43C0000 { 61 compatible = "nxp,mcux-rt-pinctrl"; 62 reg = <0x43C0000 0x4000>; 63 status = "okay"; 64 }; 65 66 ccm: ccm@4450000 { 67 compatible = "nxp,imx-ccm-rev2"; 68 reg = <0x4450000 0x4000>; 69 #clock-cells = <3>; 70 }; 71 72 lpuart1: uart@4380000 { 73 compatible = "nxp,lpuart"; 74 reg = <0x4380000 0x4000>; 75 interrupts = <19 0>; 76 clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x7c 24>; 77 status = "disabled"; 78 }; 79 80 lpuart2: uart@4390000 { 81 compatible = "nxp,lpuart"; 82 reg = <0x4390000 0x4000>; 83 interrupts = <20 0>; 84 clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x68 28>; 85 status = "disabled"; 86 }; 87 88 lpuart3: uart@2570000 { 89 compatible = "nxp,lpuart"; 90 reg = <0x2570000 0x4000>; 91 interrupts = <68 0>; 92 clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x68 12>; 93 status = "disabled"; 94 }; 95 96 lpuart4: uart@2580000 { 97 compatible = "nxp,lpuart"; 98 reg = <0x2580000 0x4000>; 99 interrupts = <69 0>; 100 clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x6c 24>; 101 status = "disabled"; 102 }; 103 104 lpuart5: uart@2590000 { 105 compatible = "nxp,lpuart"; 106 reg = <0x2590000 0x4000>; 107 interrupts = <70 0>; 108 clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 2>; 109 status = "disabled"; 110 }; 111 112 lpuart6: uart@25A0000 { 113 compatible = "nxp,lpuart"; 114 reg = <0x25A0000 0x4000>; 115 interrupts = <71 0>; 116 clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 6>; 117 status = "disabled"; 118 }; 119 120 lpuart7: uart@4570000 { 121 compatible = "nxp,lpuart"; 122 reg = <0x4570000 0x4000>; 123 interrupts = <196 0>; 124 clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x7c 26>; 125 status = "disabled"; 126 }; 127 128 lpuart8: uart@2DA0000 { 129 compatible = "nxp,lpuart"; 130 reg = <0x2DA0000 0x4000>; 131 interrupts = <197 0>; 132 clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x80 14>; 133 status = "disabled"; 134 }; 135 136 lpuart9: uart@2D70000 { 137 compatible = "nxp,lpuart"; 138 reg = <0x2D70000 0x4000>; 139 interrupts = <156 0>; 140 clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>; 141 status = "disabled"; 142 }; 143 144 lpuart10: uart@2D80000 { 145 compatible = "nxp,lpuart"; 146 reg = <0x2D80000 0x4000>; 147 interrupts = <157 0>; 148 clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>; 149 status = "disabled"; 150 }; 151 152 lpuart11: uart@2D90000 { 153 compatible = "nxp,lpuart"; 154 reg = <0x2D90000 0x4000>; 155 interrupts = <158 0>; 156 clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>; 157 status = "disabled"; 158 }; 159 160 lpuart12: uart@4580000 { 161 compatible = "nxp,lpuart"; 162 reg = <0x4580000 0x4000>; 163 interrupts = <159 0>; 164 clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>; 165 status = "disabled"; 166 }; 167 168 gpio1: gpio@7400000 { 169 compatible = "nxp,imx-rgpio"; 170 reg = <0x7400000 0x4000>; 171 interrupts = <10 0>, <11 0>; 172 gpio-controller; 173 #gpio-cells = <2>; 174 }; 175 176 gpio2: gpio@3810000 { 177 compatible = "nxp,imx-rgpio"; 178 reg = <0x3810000 0x4000>; 179 interrupts = <57 0>, <58 0>; 180 gpio-controller; 181 #gpio-cells = <2>; 182 }; 183 184 gpio3: gpio@3820000 { 185 compatible = "nxp,imx-rgpio"; 186 reg = <0x3820000 0x4000>; 187 interrupts = <59 0>, <60 0>; 188 gpio-controller; 189 #gpio-cells = <2>; 190 }; 191 192 gpio4: gpio@3830000 { 193 compatible = "nxp,imx-rgpio"; 194 reg = <0x3830000 0x4000>; 195 interrupts = <232 0>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 }; 199 200 gpio5: gpio@3840000 { 201 compatible = "nxp,imx-rgpio"; 202 reg = <0x3840000 0x4000>; 203 interrupts = <234 0>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 }; 207 208 gpio6: gpio@3850000 { 209 compatible = "nxp,imx-rgpio"; 210 reg = <0x3850000 0x4000>; 211 interrupts = <236 0>; 212 gpio-controller; 213 #gpio-cells = <2>; 214 }; 215 216 lpi2c1: i2c@4340000 { 217 compatible = "nxp,lpi2c"; 218 clock-frequency = <I2C_BITRATE_STANDARD>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x4340000 0x4000>; 222 interrupts = <13 0>; 223 clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 6>; 224 status = "disabled"; 225 }; 226 227 lpi2c2: i2c@4350000 { 228 compatible = "nxp,lpi2c"; 229 clock-frequency = <I2C_BITRATE_STANDARD>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 reg = <0x4350000 0x4000>; 233 interrupts = <14 0>; 234 clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 8>; 235 status = "disabled"; 236 }; 237 238 lpi2c3: i2c@2530000 { 239 compatible = "nxp,lpi2c"; 240 clock-frequency = <I2C_BITRATE_STANDARD>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 reg = <0x2530000 0x4000>; 244 interrupts = <62 0>; 245 clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x70 10>; 246 status = "disabled"; 247 }; 248 249 lpi2c4: i2c@2540000 { 250 compatible = "nxp,lpi2c"; 251 clock-frequency = <I2C_BITRATE_STANDARD>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 reg = <0x2540000 0x4000>; 255 interrupts = <63 0>; 256 clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x80 24>; 257 status = "disabled"; 258 }; 259 260 lpi2c5: i2c@2d30000 { 261 compatible = "nxp,lpi2c"; 262 clock-frequency = <I2C_BITRATE_STANDARD>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 reg = <0x2d30000 0x4000>; 266 interrupts = <152 0>; 267 clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>; 268 status = "disabled"; 269 }; 270 271 lpi2c6: i2c@2d40000 { 272 compatible = "nxp,lpi2c"; 273 clock-frequency = <I2C_BITRATE_STANDARD>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 reg = <0x2d40000 0x4000>; 277 interrupts = <153 0>; 278 clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>; 279 status = "disabled"; 280 }; 281 282 gpt1: gpt@46c0000 { 283 compatible = "nxp,imx-gpt"; 284 reg = <0x46c0000 0x4000>; 285 interrupts = <209 0>; 286 gptfreq = <240000000>; 287 clocks = <&ccm IMX_CCM_GPT1_CLK 0x41 0>; 288 status = "disabled"; 289 }; 290 291 gpt2: gpt@2ec0000 { 292 compatible = "nxp,imx-gpt"; 293 reg = <0x2ec0000 0x4000>; 294 interrupts = <210 0>; 295 gptfreq = <240000000>; 296 clocks = <&ccm IMX_CCM_GPT2_CLK 0x41 0>; 297 }; 298 299 acmp1: cmp@2dc0000 { 300 compatible = "nxp,kinetis-acmp"; 301 reg = <0x2dc0000 0x4000>; 302 interrupts = <200 0>; 303 status = "disabled"; 304 }; 305 306 acmp2: cmp@2dd0000 { 307 compatible = "nxp,kinetis-acmp"; 308 reg = <0x2dd0000 0x4000>; 309 interrupts = <201 0>; 310 status = "disabled"; 311 }; 312 313 acmp3: cmp@2de0000 { 314 compatible = "nxp,kinetis-acmp"; 315 reg = <0x2de0000 0x4000>; 316 interrupts = <202 0>; 317 status = "disabled"; 318 }; 319 320 acmp4: cmp@2df0000 { 321 compatible = "nxp,kinetis-acmp"; 322 reg = <0x2df0000 0x4000>; 323 interrupts = <203 0>; 324 status = "disabled"; 325 }; 326 327 lpadc1: adc@2600000 { 328 compatible = "nxp,lpc-lpadc"; 329 reg = <0x2600000 0x304>; 330 interrupts = <93 0>; 331 status = "disabled"; 332 voltage-ref= <1>; 333 calibration-average = <128>; 334 no-power-level; 335 offset-value-a = <10>; 336 offset-value-b = <10>; 337 #io-channel-cells = <1>; 338 clocks = <&ccm IMX_CCM_LPADC1_CLK 0 0>; 339 }; 340 341 lpadc2: adc@2e00000 { 342 compatible = "nxp,lpc-lpadc"; 343 reg = <0x2e00000 0x304>; 344 interrupts = <189 0>; 345 status = "disabled"; 346 clk-divider = <8>; 347 clk-source = <0>; 348 voltage-ref= <1>; 349 calibration-average = <128>; 350 no-power-level; 351 offset-value-a = <10>; 352 offset-value-b = <10>; 353 #io-channel-cells = <1>; 354 clocks = <&ccm IMX_CCM_LPADC2_CLK 0 0>; 355 }; 356 357 qtmr1: qtmr@2690000 { 358 compatible = "nxp,imx-qtmr"; 359 reg = <0x2690000 0x4000>; 360 interrupts = <0 0>; 361 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 362 qtmr1_timer0: timer0 { 363 compatible = "nxp,imx-tmr"; 364 channel = <0>; 365 status = "disabled"; 366 }; 367 qtmr1_timer1: timer1 { 368 compatible = "nxp,imx-tmr"; 369 channel = <1>; 370 status = "disabled"; 371 }; 372 qtmr1_timer2: timer2 { 373 compatible = "nxp,imx-tmr"; 374 channel = <2>; 375 status = "disabled"; 376 }; 377 qtmr1_timer3: timer3 { 378 compatible = "nxp,imx-tmr"; 379 channel = <3>; 380 status = "disabled"; 381 }; 382 }; 383 384 qtmr2: qtmr@26a0000 { 385 compatible = "nxp,imx-qtmr"; 386 reg = <0x26a0000 0x4000>; 387 interrupts = <233 0>; 388 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 389 qtmr2_timer0: timer0 { 390 compatible = "nxp,imx-tmr"; 391 channel = <0>; 392 status = "disabled"; 393 }; 394 qtmr2_timer1: timer1 { 395 compatible = "nxp,imx-tmr"; 396 channel = <1>; 397 status = "disabled"; 398 }; 399 qtmr2_timer2: timer2 { 400 compatible = "nxp,imx-tmr"; 401 channel = <2>; 402 status = "disabled"; 403 }; 404 qtmr2_timer3: timer3 { 405 compatible = "nxp,imx-tmr"; 406 channel = <3>; 407 status = "disabled"; 408 }; 409 }; 410 411 qtmr3: qtmr@26b0000 { 412 compatible = "nxp,imx-qtmr"; 413 reg = <0x26b0000 0x4000>; 414 interrupts = <164 0>; 415 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 416 qtmr3_timer0: timer0 { 417 compatible = "nxp,imx-tmr"; 418 channel = <0>; 419 status = "disabled"; 420 }; 421 qtmr3_timer1: timer1 { 422 compatible = "nxp,imx-tmr"; 423 channel = <1>; 424 status = "disabled"; 425 }; 426 qtmr3_timer2: timer2 { 427 compatible = "nxp,imx-tmr"; 428 channel = <2>; 429 status = "disabled"; 430 }; 431 qtmr3_timer3: timer3 { 432 compatible = "nxp,imx-tmr"; 433 channel = <3>; 434 status = "disabled"; 435 }; 436 }; 437 438 qtmr4: qtmr@26c0000 { 439 compatible = "nxp,imx-qtmr"; 440 reg = <0x26c0000 0x4000>; 441 interrupts = <151 0>; 442 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 443 qtmr4_timer0: timer0 { 444 compatible = "nxp,imx-tmr"; 445 channel = <0>; 446 status = "disabled"; 447 }; 448 qtmr4_timer1: timer1 { 449 compatible = "nxp,imx-tmr"; 450 channel = <1>; 451 status = "disabled"; 452 }; 453 qtmr4_timer2: timer2 { 454 compatible = "nxp,imx-tmr"; 455 channel = <2>; 456 status = "disabled"; 457 }; 458 qtmr4_timer3: timer3 { 459 compatible = "nxp,imx-tmr"; 460 channel = <3>; 461 status = "disabled"; 462 }; 463 }; 464 465 qtmr5: qtmr@26d0000 { 466 compatible = "nxp,imx-qtmr"; 467 reg = <0x26d0000 0x4000>; 468 interrupts = <4 0>; 469 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 470 qtmr5_timer0: timer0 { 471 compatible = "nxp,imx-tmr"; 472 channel = <0>; 473 status = "disabled"; 474 }; 475 qtmr5_timer1: timer1 { 476 compatible = "nxp,imx-tmr"; 477 channel = <1>; 478 status = "disabled"; 479 }; 480 qtmr5_timer2: timer2 { 481 compatible = "nxp,imx-tmr"; 482 channel = <2>; 483 status = "disabled"; 484 }; 485 qtmr5_timer3: timer3 { 486 compatible = "nxp,imx-tmr"; 487 channel = <3>; 488 status = "disabled"; 489 }; 490 }; 491 492 qtmr6: qtmr@26e0000 { 493 compatible = "nxp,imx-qtmr"; 494 reg = <0x26e0000 0x4000>; 495 interrupts = <5 0>; 496 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 497 qtmr6_timer0: timer0 { 498 compatible = "nxp,imx-tmr"; 499 channel = <0>; 500 status = "disabled"; 501 }; 502 qtmr6_timer1: timer1 { 503 compatible = "nxp,imx-tmr"; 504 channel = <1>; 505 status = "disabled"; 506 }; 507 qtmr6_timer2: timer2 { 508 compatible = "nxp,imx-tmr"; 509 channel = <2>; 510 status = "disabled"; 511 }; 512 qtmr6_timer3: timer3 { 513 compatible = "nxp,imx-tmr"; 514 channel = <3>; 515 status = "disabled"; 516 }; 517 }; 518 519 qtmr7: qtmr@26f0000 { 520 compatible = "nxp,imx-qtmr"; 521 reg = <0x26f0000 0x4000>; 522 interrupts = <6 0>; 523 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 524 qtmr7_timer0: timer0 { 525 compatible = "nxp,imx-tmr"; 526 channel = <0>; 527 status = "disabled"; 528 }; 529 qtmr7_timer1: timer1 { 530 compatible = "nxp,imx-tmr"; 531 channel = <1>; 532 status = "disabled"; 533 }; 534 qtmr7_timer2: timer2 { 535 compatible = "nxp,imx-tmr"; 536 channel = <2>; 537 status = "disabled"; 538 }; 539 qtmr7_timer3: timer3 { 540 compatible = "nxp,imx-tmr"; 541 channel = <3>; 542 status = "disabled"; 543 }; 544 }; 545 546 qtmr8: qtmr@2700000 { 547 compatible = "nxp,imx-qtmr"; 548 reg = <0x2700000 0x4000>; 549 interrupts = <7 0>; 550 clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; 551 qtmr8_timer0: timer0 { 552 compatible = "nxp,imx-tmr"; 553 channel = <0>; 554 status = "disabled"; 555 }; 556 qtmr8_timer1: timer1 { 557 compatible = "nxp,imx-tmr"; 558 channel = <1>; 559 status = "disabled"; 560 }; 561 qtmr8_timer2: timer2 { 562 compatible = "nxp,imx-tmr"; 563 channel = <2>; 564 status = "disabled"; 565 }; 566 qtmr8_timer3: timer3 { 567 compatible = "nxp,imx-tmr"; 568 channel = <3>; 569 status = "disabled"; 570 }; 571 }; 572 573 netc: ethernet@60000000 { 574 reg = <0x60000000 0x1000000>; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 ranges; 578 579 enetc_psi0: ethernet@60b00000 { 580 compatible = "nxp,imx-netc-psi"; 581 reg = <0x60b00000 0x10000>; 582 mac-index = <0>; 583 si-index = <0>; 584 status = "disabled"; 585 }; 586 587 enetc_psi1: ethernet@60b40000 { 588 compatible = "nxp,imx-netc-psi"; 589 reg = <0x60b40000 0x10000>; 590 mac-index = <1>; 591 si-index = <1>; 592 status = "disabled"; 593 }; 594 595 emdio: mdio@60ba0000 { 596 compatible = "nxp,imx-netc-emdio"; 597 reg = <0x60ba0000 0x1c44>; 598 clocks = <&ccm IMX_CCM_NETC_CLK 0x0 0>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 }; 604 605 flexcan1: can@43a0000 { 606 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 607 reg = <0x43a0000 0x1000>; 608 interrupts = <8 0>, <9 0>; 609 interrupt-names = "common", "error"; 610 clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; 611 clk-source = <0>; 612 status = "disabled"; 613 }; 614 615 flexcan2: can@25b0000 { 616 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 617 reg = <0x25b0000 0x1000>; 618 interrupts = <51 0>, <52 0>; 619 interrupt-names = "common", "error"; 620 clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>; 621 clk-source = <0>; 622 status = "disabled"; 623 }; 624 625 flexcan3: can@45b0000 { 626 compatible = "nxp,flexcan-fd", "nxp,flexcan"; 627 reg = <0x45b0000 0x1000>; 628 interrupts = <191 0>, <192 0>; 629 interrupt-names = "common", "error"; 630 clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>; 631 clk-source = <0>; 632 status = "disabled"; 633 }; 634 635 lptmr1: lptmr@4300000 { 636 compatible = "nxp,lptmr"; 637 reg = <0x4300000 0x1000>; 638 interrupts = <18 0>; 639 clock-frequency = <80000000>; 640 prescaler = <1>; 641 clk-source = <0>; 642 resolution = <32>; 643 status = "disabled"; 644 }; 645 646 lptmr2: lptmr@24d0000 { 647 compatible = "nxp,lptmr"; 648 reg = <0x24d0000 0x1000>; 649 interrupts = <67 0>; 650 clock-frequency = <80000000>; 651 prescaler = <1>; 652 clk-source = <0>; 653 resolution = <32>; 654 status = "disabled"; 655 }; 656 657 lptmr3: lptmr@2cd0000 { 658 compatible = "nxp,lptmr"; 659 reg = <0x2cd0000 0x1000>; 660 interrupts = <150 0>; 661 clock-frequency = <80000000>; 662 prescaler = <1>; 663 clk-source = <0>; 664 resolution = <32>; 665 status = "disabled"; 666 }; 667 668 flexpwm1: flexpwm@2650000 { 669 compatible = "nxp,flexpwm"; 670 reg = <0x2650000 0x4000>; 671 interrupts = <23 0>; 672 673 flexpwm1_pwm0: flexpwm1_pwm0 { 674 compatible = "nxp,imx-pwm"; 675 index = <0>; 676 interrupts = <24 0>; 677 #pwm-cells = <3>; 678 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 679 nxp,prescaler = <128>; 680 status = "disabled"; 681 }; 682 683 flexpwm1_pwm1: flexpwm1_pwm1 { 684 compatible = "nxp,imx-pwm"; 685 index = <1>; 686 interrupts = <25 0>; 687 #pwm-cells = <3>; 688 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 689 nxp,prescaler = <128>; 690 status = "disabled"; 691 }; 692 693 flexpwm1_pwm2: flexpwm1_pwm2 { 694 compatible = "nxp,imx-pwm"; 695 index = <2>; 696 interrupts = <26 0>; 697 #pwm-cells = <3>; 698 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 699 nxp,prescaler = <128>; 700 status = "disabled"; 701 }; 702 703 flexpwm1_pwm3: flexpwm1_pwm3 { 704 compatible = "nxp,imx-pwm"; 705 index = <3>; 706 interrupts = <27 0>; 707 #pwm-cells = <3>; 708 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 709 nxp,prescaler = <128>; 710 status = "disabled"; 711 }; 712 }; 713 714 flexpwm2: flexpwm@2660000 { 715 compatible = "nxp,flexpwm"; 716 reg = <0x2660000 0x4000>; 717 interrupts = <170 0>; 718 719 flexpwm2_pwm0: flexpwm2_pwm0 { 720 compatible = "nxp,imx-pwm"; 721 index = <0>; 722 interrupts = <171 0>; 723 #pwm-cells = <3>; 724 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 725 nxp,prescaler = <128>; 726 status = "disabled"; 727 }; 728 729 flexpwm2_pwm1: flexpwm2_pwm1 { 730 compatible = "nxp,imx-pwm"; 731 index = <1>; 732 interrupts = <172 0>; 733 #pwm-cells = <3>; 734 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 735 nxp,prescaler = <128>; 736 status = "disabled"; 737 }; 738 739 flexpwm2_pwm2: flexpwm2_pwm2 { 740 compatible = "nxp,imx-pwm"; 741 index = <2>; 742 interrupts = <173 0>; 743 #pwm-cells = <3>; 744 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 745 nxp,prescaler = <128>; 746 status = "disabled"; 747 }; 748 749 flexpwm2_pwm3: flexpwm2_pwm3 { 750 compatible = "nxp,imx-pwm"; 751 index = <3>; 752 interrupts = <174 0>; 753 #pwm-cells = <3>; 754 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 755 nxp,prescaler = <128>; 756 status = "disabled"; 757 }; 758 }; 759 760 flexpwm3: flexpwm@2670000 { 761 compatible = "nxp,flexpwm"; 762 reg = <0x2670000 0x4000>; 763 interrupts = <175 0>; 764 765 flexpwm3_pwm0: flexpwm3_pwm0 { 766 compatible = "nxp,imx-pwm"; 767 index = <0>; 768 interrupts = <176 0>; 769 #pwm-cells = <3>; 770 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 771 nxp,prescaler = <128>; 772 status = "disabled"; 773 }; 774 775 flexpwm3_pwm1: flexpwm3_pwm1 { 776 compatible = "nxp,imx-pwm"; 777 index = <1>; 778 interrupts = <177 0>; 779 #pwm-cells = <3>; 780 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 781 nxp,prescaler = <128>; 782 status = "disabled"; 783 }; 784 785 flexpwm3_pwm2: flexpwm3_pwm2 { 786 compatible = "nxp,imx-pwm"; 787 index = <2>; 788 interrupts = <178 0>; 789 #pwm-cells = <3>; 790 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 791 nxp,prescaler = <128>; 792 status = "disabled"; 793 }; 794 795 flexpwm3_pwm3: flexpwm3_pwm3 { 796 compatible = "nxp,imx-pwm"; 797 index = <3>; 798 interrupts = <179 0>; 799 #pwm-cells = <3>; 800 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 801 nxp,prescaler = <128>; 802 status = "disabled"; 803 }; 804 }; 805 806 flexpwm4: flexpwm@2680000 { 807 compatible = "nxp,flexpwm"; 808 reg = <0x2680000 0x4000>; 809 interrupts = <180 0>; 810 811 flexpwm4_pwm0: flexpwm4_pwm0 { 812 compatible = "nxp,imx-pwm"; 813 index = <0>; 814 interrupts = <181 0>; 815 #pwm-cells = <3>; 816 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 817 nxp,prescaler = <128>; 818 status = "disabled"; 819 }; 820 821 flexpwm4_pwm1: flexpwm4_pwm1 { 822 compatible = "nxp,imx-pwm"; 823 index = <1>; 824 interrupts = <182 0>; 825 #pwm-cells = <3>; 826 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 827 nxp,prescaler = <128>; 828 status = "disabled"; 829 }; 830 831 flexpwm4_pwm2: flexpwm4_pwm2 { 832 compatible = "nxp,imx-pwm"; 833 index = <2>; 834 interrupts = <183 0>; 835 #pwm-cells = <3>; 836 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 837 nxp,prescaler = <128>; 838 status = "disabled"; 839 }; 840 841 flexpwm4_pwm3: flexpwm4_pwm3 { 842 compatible = "nxp,imx-pwm"; 843 index = <3>; 844 interrupts = <184 0>; 845 #pwm-cells = <3>; 846 clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; 847 nxp,prescaler = <128>; 848 status = "disabled"; 849 }; 850 }; 851 852 tpm1: pwm@4310000 { 853 compatible = "nxp,kinetis-tpm"; 854 reg = <0x4310000 0x88>; 855 interrupts = <36 0>; 856 clocks = <&ccm IMX_CCM_TPM1_CLK 0x3b 0>; 857 prescaler = <16>; 858 status = "disabled"; 859 #pwm-cells = <3>; 860 }; 861 862 tpm2: pwm@4320000 { 863 compatible = "nxp,kinetis-tpm"; 864 reg = <0x4320000 0x88>; 865 interrupts = <37 0>; 866 clocks = <&ccm IMX_CCM_TPM2_CLK 0x3c 0>; 867 prescaler = <16>; 868 status = "disabled"; 869 #pwm-cells = <3>; 870 }; 871 872 tpm3: pwm@24E0000 { 873 compatible = "nxp,kinetis-tpm"; 874 reg = <0x24E0000 0x88>; 875 interrupts = <75 0>; 876 clocks = <&ccm IMX_CCM_TPM3_CLK 0x3d 0>; 877 prescaler = <16>; 878 status = "disabled"; 879 #pwm-cells = <3>; 880 }; 881 882 tpm4: pwm@24F0000 { 883 compatible = "nxp,kinetis-tpm"; 884 reg = <0x24F0000 0x88>; 885 interrupts = <76 0>; 886 clocks = <&ccm IMX_CCM_TPM4_CLK 0x3e 0>; 887 prescaler = <16>; 888 status = "disabled"; 889 #pwm-cells = <3>; 890 }; 891 892 tpm5: pwm@2500000 { 893 compatible = "nxp,kinetis-tpm"; 894 reg = <0x2500000 0x88>; 895 interrupts = <77 0>; 896 clocks = <&ccm IMX_CCM_TPM5_CLK 0x3f 0>; 897 prescaler = <16>; 898 status = "disabled"; 899 #pwm-cells = <3>; 900 }; 901 902 tpm6: pwm@42510000 { 903 compatible = "nxp,kinetis-tpm"; 904 reg = <0x42510000 0x88>; 905 interrupts = <78 0>; 906 clocks = <&ccm IMX_CCM_TPM6_CLK 0x40 0>; 907 prescaler = <16>; 908 status = "disabled"; 909 #pwm-cells = <3>; 910 }; 911 912 i3c1: i3c@4330000 { 913 compatible = "nxp,mcux-i3c"; 914 reg = <0x4330000 0x1000>; 915 interrupts = <12 0>; 916 clocks = <&ccm IMX_CCM_I3C1_CLK 0x67 0>; 917 clk-divider = <2>; 918 clk-divider-slow = <1>; 919 clk-divider-tc = <1>; 920 status = "disabled"; 921 #address-cells = <3>; 922 #size-cells = <0>; 923 }; 924 925 i3c2: i3c@2520000 { 926 compatible = "nxp,mcux-i3c"; 927 reg = <0x2520000 0x1000>; 928 interrupts = <61 0>; 929 clocks = <&ccm IMX_CCM_I3C2_CLK 0x68 0>; 930 clk-divider = <2>; 931 clk-divider-slow = <1>; 932 clk-divider-tc = <1>; 933 status = "disabled"; 934 #address-cells = <3>; 935 #size-cells = <0>; 936 }; 937}; 938 939&flexspi { 940 compatible = "nxp,imx-flexspi"; 941 interrupts = <55 0>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 status = "disabled"; 945 clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>; 946}; 947 948&flexspi2 { 949 compatible = "nxp,imx-flexspi"; 950 interrupts = <56 0>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 status = "disabled"; 954 clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0>; 955}; 956 957&memory { 958 #address-cells = <1>; 959 #size-cells = <1>; 960 ocram1: ocram@484000 { 961 compatible = "zephyr,memory-region", "mmio-sram"; 962 zephyr,memory-region = "OCRAM1"; 963 /* OCRAM1 first 16K access is blocked by TRDC */ 964 reg = <0x484000 DT_SIZE_K(496)>; 965 }; 966 967 ocram2: ocram@500000 { 968 compatible = "zephyr,memory-region", "mmio-sram"; 969 zephyr,memory-region = "OCRAM2"; 970 reg = <0x500000 DT_SIZE_K(256)>; 971 }; 972}; 973
