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/Zephyr-latest/dts/bindings/phy/
Drenesas,ra-usbphyc.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA USBHS internal PHY controller
6 compatible: "renesas,ra-usbphyc"
8 include: phy-controller.yaml
11 clock:
14 Clock source for PHY clock in case internal clock is using
16 phys-clock-src:
19 - "internal"
20 - "xtal"
22 Select clock source for PHY clock as XTAL or use internal clock
[all …]
Dst,stm32u5-otghs-phy.yaml3 # SPDX-License-Identifier: Apache-2.0
6 This binding is to be used by the STM32U5xx transceivers which are built-in
7 with USB HS PHY IP and a configurable HSE clock source.
9 compatible: "st,stm32u5-otghs-phy"
11 include: phy-controller.yaml
14 "#phy-cells":
/Zephyr-latest/drivers/ethernet/nxp_enet/
DKconfig3 # Copyright (c) 2016-2017 ARM Ltd
5 # SPDX-License-Identifier: Apache-2.0
36 Note, this driver performs one shot PHY setup.
37 There is no support for PHY disconnect, reconnect or configuration change.
62 - IPv4, UDP and TCP checksum (both Rx and Tx)
113 - IPv4, UDP and TCP checksum (both Rx and Tx)
132 bool "RMII clock from external sources"
134 Setting this option will configure MCUX clock block to feed RMII
135 reference clock from external source (ENET_1588_CLKIN)
138 bool "Do not use SMI for PHY communication"
[all …]
/Zephyr-latest/dts/bindings/mipi-dsi/
Dmipi-dsi-host.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI-DSI hosts
8 bus: mipi-dsi
11 "#address-cells":
15 "#size-cells":
19 phy-clock:
22 MIPI PHY clock frequency. Should be set to ensure clock frequency is at
23 least (pixel clock * bits per output pixel) / number of mipi data lanes
Dst,stm32-mipi-dsi.yaml4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32-mipi-dsi"
11 include: [mipi-dsi-host.yaml, reset-device.yaml]
17 clock-names:
20 "dsiclk" DSI clock enable.
21 "refclk" External crystal or oscillator clock.
22 "pixelclk" LTDC pixel clock.
28 hs-active-high:
33 vs-active-high:
38 de-active-high:
[all …]
/Zephyr-latest/boards/silabs/starter_kits/slstk3701a/
Dboard.c5 * SPDX-License-Identifier: Apache-2.0
19 /* Enable the ethernet PHY power */ in efm32gg_stk3701a_init()
22 printk("Ethernet PHY power gpio port is not ready!\n"); in efm32gg_stk3701a_init()
23 return -ENODEV; in efm32gg_stk3701a_init()
29 /* Configure ethernet reference clock */ in efm32gg_stk3701a_init()
32 printk("Ethernet reference clock gpio port is not ready!\n"); in efm32gg_stk3701a_init()
33 return -ENODEV; in efm32gg_stk3701a_init()
41 /* enable CMU_CLK2 as RMII reference clock */ in efm32gg_stk3701a_init()
42 CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO; in efm32gg_stk3701a_init()
43 CMU->ROUTELOC0 = (CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK) | in efm32gg_stk3701a_init()
[all …]
/Zephyr-latest/dts/bindings/ethernet/
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
23 Specifies the base clock frequency from which the GEM's TX clock
25 clock control register in the CRL_APB. The GEM's TX clock frequency
26 is determined by the current link speed reported by the PHY, to
27 which it will be adjusted at run-time. Therefore, the value of this
28 item must be set to the clock frequency of the PLL supplying the
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
[all …]
Dsilabs,gecko-ethernet.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "silabs,gecko-ethernet"
9 include: ethernet-controller.yaml
20 # PHY address
21 phy-address:
24 description: address of the PHY on the MDIO bus
27 location-rmii:
32 # PHY management interface location
33 location-mdio:
38 # PHY management pins
[all …]
/Zephyr-latest/boards/segger/ip_k66f/
Dip_k66f.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "ip_k66f-pinctrl.dtsi"
20 dsa-spi = &spi1;
26 zephyr,code-partition = &slot0_partition;
30 compatible = "gpio-leds";
44 clock-frequency = <120000000>;
48 pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
49 er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
52 clock-div = <3>;
[all …]
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/lll/
Dlll_vendor.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
12 /* Worst-case time margin needed after event end-time in the air
13 * (done/preempt race margin + power-down/chain delay)
20 * clock.
24 #define EVENT_RX_JITTER_US(phy) 16 /* Radio Rx timing uncertainty */ argument
25 #define EVENT_RX_TO_US(phy) ((((((phy)&0x03) + 4)<<3)/BIT((((phy)&0x3)>>1))) + \ argument
26 EVENT_RX_JITTER_US(phy))
28 /* TODO - fix up numbers re. HW */
29 #define EVENT_RX_TX_TURNAROUND(phy) ((phy) == 1?100:((phy) == 2 ? 80:900)) argument
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/lll/
Dlll_vendor.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
22 * PHY, scheduling and receiving auxiliary PDUs.
42 /* Worst-case time margin needed after event end-time in the air
43 * (done/preempt race margin + power-down/chain delay)
47 /* Sleep Clock Accuracy */
50 /* Inter-Event Space (IES) */
56 * clock.
61 #define EVENT_RX_JITTER_US(phy) 16 /* Radio Rx timing uncertainty */ argument
62 #define EVENT_RX_TO_US(phy) ((((((phy)&0x03) + 4)<<3)/BIT((((phy)&0x3)>>1))) + \ argument
[all …]
/Zephyr-latest/boards/espressif/esp32_ethernet_kit/doc/
Dindex.rst6 The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables
7 Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide
8 more flexible power supply options, the ESP32-Ethernet-Kit also supports power
11 .. _get-started-esp32-ethernet-kit-v1.2-overview:
13 ESP32-Ethernet-Kit is an ESP32-WROVER-E based development.
14 For more information, check the datasheet at `ESP32-WROVER-E Datasheet`_.
17 board B. The `Ethernet Board (A)`_ contains Bluetooth/Wi-Fi dual-mode
18 ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet
19 Transceiver (PHY). The `PoE Board (B)`_ provides power over Ethernet
23 .. _get-started-esp32-ethernet-kit-v1.2:
[all …]
/Zephyr-latest/dts/arm64/fvp/
Dfvp-aemv8r.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm64/armv8-r.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-r82";
23 compatible = "arm,cortex-r82";
29 compatible = "arm,cortex-r82";
35 compatible = "arm,cortex-r82";
41 compatible = "arm,armv8-timer";
[all …]
/Zephyr-latest/boards/atmel/sam0/same54_xpro/
Dsame54_xpro.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include "same54_xpro-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &sercom2;
26 pwm-led0 = &pwm_led0;
28 i2c-0 = &sercom7;
32 compatible = "gpio-leds";
40 compatible = "pwm-leds";
47 compatible = "gpio-keys";
[all …]
/Zephyr-latest/drivers/ethernet/
DKconfig.stm32_hal5 # SPDX-License-Identifier: Apache-2.0
68 int "Phy address"
71 The phy address to use.
84 PHY's carrier status is re-evaluated.
119 bool "STM32 HAL PTP clock driver support"
123 Enable STM32 PTP clock support.
126 int "Frequency of the clock source for the PTP timer"
134 int "Lower bound of clock frequency adjustment (in percent)"
138 Specifies lower bound of PTP clock rate adjustment.
141 int "Upper bound of clock frequency adjustment (in percent)"
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4ma0/boards/
Dmimxrt1160_evk_mimxrt1166_cm7.overlay4 * SPDX-License-Identifier: Apache-2.0
8 /* Raise the DSI clock frequency */
9 phy-clock = <792000000>;
Dmimxrt1170_evk_mimxrt1176_cm7.overlay4 * SPDX-License-Identifier: Apache-2.0
8 /* Raise the DSI clock frequency */
9 phy-clock = <792000000>;
/Zephyr-latest/boards/renesas/mck_ra8t1/
Dmck_ra8t1.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include "mck_ra8t1-pinctrl.dtsi"
14 model = "Renesas MCK-RA8T1";
21 zephyr,shell-uart = &uart3;
23 zephyr,flash-controller = &flash1;
28 compatible = "gpio-leds";
54 clock-frequency = <DT_FREQ_M(24)>;
[all …]
/Zephyr-latest/boards/nxp/imx93_evk/
Dimx93_evk_mimx9352_a55.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "imx93_evk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 zephyr,shell-uart = &lpuart2;
42 compatible = "gpio-leds";
58 compatible = "gpio-keys";
73 board_exp_sel: board-exp-sel {
78 compatible = "imx93evk-exp-sel";
79 mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/
Dfvp_base_revc_2xaemv8a.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
23 zephyr,shell-uart = &uart0;
27 compatible = "arm,psci-0.2";
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a53";
43 compatible = "arm,cortex-a53";
[all …]
/Zephyr-latest/boards/nxp/s32z2xxdc2/
Ds32z2xxdc2_s32z270.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
14 pinctrl-0 = <&emdio_default>;
15 pinctrl-names = "default";
18 phy0: ethernet-phy@7 {
19 compatible = "ethernet-phy";
26 local-mac-address = [00 00 00 01 02 00];
27 pinctrl-0 = <&eth0_default>;
28 pinctrl-names = "default";
29 clock-frequency = <300000000>;
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4ma0/
Drk055hdmipi4ma0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
30 gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4m/
Drk055hdmipi4m.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display: enable-mipi-display {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
34 reset-gpios = <&nxp_mipi_connector 28 GPIO_ACTIVE_LOW>;
[all …]
/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
7 /* Port 0~4 PHY Control Register. */
44 /* Address Table Control And Status Register PHY Address */
74 /* Address Table Data 0 PHY Address */
81 /* Address Table Data 1 PHY Address */
86 /* Address Table Data 2 PHY Address */
91 /* Address Table Data 3 PHY Address */
96 /* Address Table Data 4 PHY Address */
101 /* WoL Control Register PHY Address */
106 /* PHY address 0x18h */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h2 * Copyright (c) 2021-2022, Weidmueller Interface GmbH & Co. KG
3 * SPDX-License-Identifier: Apache-2.0
9 /* PHY auto-detection alias */
17 * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
18 * as it claims that the MDC clock division is applied to the cpu_1x clock
21 * the PHY", p. 1074, that the MDC clock division is applied to the IOU_SWITCH_CLK.
23 * on the UltraScale compared to the Zynq-7000.
24 * -> Contrary to earlier revisions of this driver, all dividers are available
25 * to both the UltraScale and the Zynq-7000.
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
[all …]

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