1/*
2 * Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/dts-v1/;
7
8#include <mem.h>
9#include <arm64/armv8-a.dtsi>
10#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	model = "FVP Base RevC 2xAEMv8A";
14
15	chosen {
16		/*
17		 * The SRAM node is actually located in the
18		 * DRAM region of the FVP Base RevC 2xAEMv8A.
19		 */
20		zephyr,sram = &dram0;
21		zephyr,flash = &flash0;
22		zephyr,console = &uart0;
23		zephyr,shell-uart = &uart0;
24	};
25
26	psci {
27		compatible = "arm,psci-0.2";
28		method = "smc";
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu@0 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53";
38			reg = <0>;
39		};
40
41		cpu@100 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			reg = <0x100>;
45		};
46
47		cpu@200 {
48			device_type = "cpu";
49			compatible = "arm,cortex-a53";
50			reg = <0x200>;
51		};
52
53		cpu@300 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a53";
56			reg = <0x300>;
57		};
58	};
59
60	timer {
61		compatible = "arm,armv8-timer";
62		interrupt-parent = <&gic>;
63		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
64			      IRQ_DEFAULT_PRIORITY>,
65			     <GIC_PPI 14 IRQ_TYPE_LEVEL
66			      IRQ_DEFAULT_PRIORITY>,
67			     <GIC_PPI 11 IRQ_TYPE_LEVEL
68			      IRQ_DEFAULT_PRIORITY>,
69			     <GIC_PPI 10 IRQ_TYPE_LEVEL
70			      IRQ_DEFAULT_PRIORITY>;
71	};
72
73	uartclk: apb-pclk {
74		compatible = "fixed-clock";
75		clock-frequency = <24000000>;
76		#clock-cells = <0>;
77	};
78
79	soc {
80		interrupt-parent = <&gic>;
81
82		gic: interrupt-controller@2f000000 {
83			compatible = "arm,gic-v3", "arm,gic";
84			reg = <0x2f000000 0x10000>, // GICD
85			      <0x2f100000 0x200000>; // GICR
86			interrupt-controller;
87			#interrupt-cells = <4>;
88			status = "okay";
89			#address-cells = <1>;
90			#size-cells = <1>;
91
92			its: msi-controller@2f020000 {
93				compatible = "arm,gic-v3-its";
94				reg = <0x2f020000 0x20000>;
95				status = "okay";
96			};
97		};
98
99		uart0: uart@1c090000 {
100			compatible = "arm,pl011";
101			reg = <0x1c090000 0x1000>;
102			status = "disabled";
103			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
104			interrupt-names = "irq_5";
105			clocks = <&uartclk>;
106		};
107
108		uart1: uart@1c0a0000 {
109			compatible = "arm,pl011";
110			reg = <0x1c0a0000 0x1000>;
111			status = "disabled";
112			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
113			interrupt-names = "irq_6";
114			clocks = <&uartclk>;
115		};
116
117		uart2: uart@1c0b0000 {
118			compatible = "arm,pl011";
119			reg = <0x1c0b0000 0x1000>;
120			status = "disabled";
121			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
122			interrupt-names = "irq_7";
123			clocks = <&uartclk>;
124		};
125
126		uart3: uart@1c0c0000 {
127			compatible = "arm,pl011";
128			reg = <0x1c0c0000 0x1000>;
129			status = "disabled";
130			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
131			interrupt-names = "irq_8";
132			clocks = <&uartclk>;
133		};
134
135		ethernet@1a000000 {
136			reg = <0x1a000000 0x1000>;
137
138			eth: ethernet {
139				compatible = "smsc,lan91c111";
140				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
141				status = "disabled";
142
143				phy-handle = <&phy>;
144			};
145
146			mdio: mdio {
147				compatible = "smsc,lan91c111-mdio";
148				status = "disabled";
149				#address-cells = <1>;
150				#size-cells = <0>;
151
152				phy: ethernet-phy@0 {
153					compatible = "ethernet-phy";
154					status = "disabled";
155					reg = <0>;
156				};
157			};
158		};
159
160		flash0: flash@0 {
161			compatible = "soc-nv-flash";
162			reg = <0x0 DT_SIZE_K(64)>;
163		};
164
165		dram0: memory@88000000 {
166			compatible = "mmio-dram";
167			reg = <0x88000000 DT_SIZE_K(2048)>;
168		};
169	};
170};
171
172&uart0 {
173	status = "okay";
174	current-speed = <115200>;
175};
176