Lines Matching +full:phy +full:- +full:clock

4  * SPDX-License-Identifier: Apache-2.0
7 /* Port 0~4 PHY Control Register. */
44 /* Address Table Control And Status Register PHY Address */
74 /* Address Table Data 0 PHY Address */
81 /* Address Table Data 1 PHY Address */
86 /* Address Table Data 2 PHY Address */
91 /* Address Table Data 3 PHY Address */
96 /* Address Table Data 4 PHY Address */
101 /* WoL Control Register PHY Address */
106 /* PHY address 0x18h */
109 /* Interrupt Status Register PHY Address. */
114 /* Interrupt Mask & Control Register PHY Address. */
131 /* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5
135 /* Port 5 Clock Source Selection control bit. Only available when Port 5
145  * 100M link fail                       - LED off
146  * 100M link ok and no TX/RX activity   - LED on
147  * 100M link ok and TX/RX activity      - LED blinking
149  * No colision:                         - LED off
150  * Colision:                            - LED blinking
152  * 10M link fail                        - LED off
153  * 10M link ok and no TX/RX activity    - LED on
154  * 10M link ok and TX/RX activity       - LED blinking