1 /* 2 * Copyright (c) 2024 Robert Slawinski <robert.slawinski1@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* Port 0~4 PHY Control Register. */ 8 #define PORTX_PHY_CONTROL_REGISTER 0x0u 9 /* 10 Mbit/s transfer with half duplex mask. */ 10 #define MODE_10_BASET_HALF_DUPLEX 0x0u 11 /* 10 Mbit/s transfer with full duplex mask. */ 12 #define MODE_10_BASET_FULL_DUPLEX 0x100u 13 /* 100 Mbit/s transfer with half duplex mask. */ 14 #define MODE_100_BASET_HALF_DUPLEX 0x2000u 15 /* 100 Mbit/s transfer with full duplex mask. */ 16 #define MODE_100_BASET_FULL_DUPLEX 0x2100u 17 /* Duplex mode ability offset. */ 18 #define DUPLEX_MODE (1 << 8) 19 /* Power down mode offset. */ 20 #define POWER_DOWN (1 << 11) 21 /* Auto negotiation mode offset. */ 22 #define AUTO_NEGOTIATION (1 << 12) 23 /* Link speed selection offset. */ 24 #define LINK_SPEED (1 << 13) 25 26 /* Port 0~4 Status Data Register. */ 27 #define PORTX_SWITCH_STATUS 0x10u 28 /* 10 Mbit/s transfer speed with half duplex. */ 29 #define SPEED_10MBPS_HALF_DUPLEX 0x00u 30 /* 10 Mbit/s transfer speed with full duplex. */ 31 #define SPEED_10MBPS_FULL_DUPLEX 0x01u 32 /* 100 Mbit/s transfer speed with half duplex. */ 33 #define SPEED_100MBPS_HALF_DUPLEX 0x02u 34 /* 100 Mbit/s transfer speed with full duplex. */ 35 #define SPEED_100MBPS_FULL_DUPLEX 0x03u 36 /* Speed and duplex mode status offset. */ 37 #define SPEED_AND_DUPLEX_OFFSET 0x01u 38 /* Speed and duplex mode staus mask. */ 39 #define SPEED_AND_DUPLEX_MASK 0x07u 40 /* Link status mask. */ 41 #define LINK_STATUS_MASK 0x1u 42 43 /* Switch Engine Registers */ 44 /* Address Table Control And Status Register PHY Address */ 45 #define ADDR_TAB_CTRL_STAT_PHY_ADDR 0x15u 46 /* Address Table Control And Status Register Register SAddress */ 47 #define ADDR_TAB_CTRL_STAT_REG_ADDR 0x10u 48 49 /* Address Table Access bussy flag offset */ 50 #define ATB_S_OFFSET 0xf 51 /* Address Table Command Result flag offset */ 52 #define ATB_CR_OFFSET 0xd 53 /* Address Table Command Result flag mask */ 54 #define ATB_CR_MASK 0x3 55 56 /* Unicast Address Table Index*/ 57 #define UNICAST_ADDR_TAB (1 << 0 | 1 << 1) 58 /* Multicast Address Table Index*/ 59 #define MULTICAST_ADDR_TAB (1 << 0) 60 /* IGMP Table Index*/ 61 #define IGMP_ADDR_TAB (1 << 1) 62 63 /* Read a entry with sequence number of address table */ 64 #define ATB_CMD_READ (1 << 2 | 1 << 3 | 1 << 4) 65 /* Write a entry with MAC address */ 66 #define ATB_CMD_WRITE (1 << 2) 67 /* Delete a entry with MAC address */ 68 #define ATB_CMD_DELETE (1 << 3) 69 /* Search a entry with MAC address */ 70 #define ATB_CMD_SEARCH (1 << 2 | 1 << 3) 71 /* Clear one or more than one entries with Port or FID */ 72 #define ATB_CMD_CLEAR (1 << 4) 73 74 /* Address Table Data 0 PHY Address */ 75 #define ADDR_TAB_DATA0_PHY_ADDR 0x15u 76 /* Address Table Data 0 Register Address */ 77 #define ADDR_TAB_DATA0_REG_ADDR 0x11u 78 /* Port number or port map mask*/ 79 #define ATB_PORT_MASK 0x1f 80 81 /* Address Table Data 1 PHY Address */ 82 #define ADDR_TAB_DATA1_PHY_ADDR 0x15u 83 /* Address Table Data 1 Register Address */ 84 #define ADDR_TAB_DATA1_REG_ADDR 0x12u 85 86 /* Address Table Data 2 PHY Address */ 87 #define ADDR_TAB_DATA2_PHY_ADDR 0x15u 88 /* Address Table Data 2 Register Address */ 89 #define ADDR_TAB_DATA2_REG_ADDR 0x13u 90 91 /* Address Table Data 3 PHY Address */ 92 #define ADDR_TAB_DATA3_PHY_ADDR 0x15u 93 /* Address Table Data 3 Register Address */ 94 #define ADDR_TAB_DATA3_REG_ADDR 0x14u 95 96 /* Address Table Data 4 PHY Address */ 97 #define ADDR_TAB_DATA4_PHY_ADDR 0x15u 98 /* Address Table Data 4 Register Address */ 99 #define ADDR_TAB_DATA4_REG_ADDR 0x15u 100 101 /* WoL Control Register PHY Address */ 102 #define WOLL_CTRL_REG_PHY_ADDR 0x15u 103 /* WoL Control Register Register Address */ 104 #define WOLL_CTRL_REG_REG_ADDR 0x1bu 105 106 /* PHY address 0x18h */ 107 #define PHY_ADDRESS_18H 0x18u 108 109 /* Interrupt Status Register PHY Address. */ 110 #define INT_STAT_PHY_ADDR 0x18u 111 /* Interrupt Status Register Register Address. */ 112 #define INT_STAT_REG_ADDR 0x18u 113 114 /* Interrupt Mask & Control Register PHY Address. */ 115 #define INT_MASK_CTRL_PHY_ADDR 0x18u 116 /* Interrupt Mask & Control Register Register Address. */ 117 #define INT_MASK_CTRL_REG_ADDR 0x19u 118 119 #define PORT5_MAC_CONTROL 0x15u 120 /* Port 5 Force Speed control bit */ 121 #define P5_SPEED_100M ~BIT(0) 122 /* Port 5 Force Duplex control bit */ 123 #define P5_FULL_DUPLEX ~BIT(1) 124 /* Port 5 Force Link control bit. Only available in force mode. */ 125 #define P5_FORCE_LINK_ON ~BIT(2) 126 /* Port 5 Force Mode Enable control bit. Only available for 127 * MII/RevMII/RMII 128 */ 129 #define P5_EN_FORCE BIT(3) 130 /* Bit 4 is reserved and should not be use */ 131 /* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5 132 * be configured as RMII 133 */ 134 #define P5_50M_CLK_OUT_ENABLE BIT(5) 135 /* Port 5 Clock Source Selection control bit. Only available when Port 5 136 * is configured as RMII 137 */ 138 #define P5_50M_INT_CLK_SOURCE BIT(6) 139 /* Port 5 Output Pin Slew Rate. */ 140 #define P5_NORMAL_SLEW_RATE ~BIT(7) 141 /* IRQ and LED Control Register. */ 142 #define IRQ_LED_CONTROL 0x17u 143 /* LED mode 0: 144 * LNK_LED: 145 * 100M link fail - LED off 146 * 100M link ok and no TX/RX activity - LED on 147 * 100M link ok and TX/RX activity - LED blinking 148 * SPD_LED: 149 * No colision: - LED off 150 * Colision: - LED blinking 151 * FDX_LED: 152 * 10M link fail - LED off 153 * 10M link ok and no TX/RX activity - LED on 154 * 10M link ok and TX/RX activity - LED blinking 155 */ 156 #define LED_MODE_0 ~(BIT(0) | BIT(1)) 157
