Lines Matching +full:phy +full:- +full:clock
2 * Copyright (c) 2021-2022, Weidmueller Interface GmbH & Co. KG
3 * SPDX-License-Identifier: Apache-2.0
9 /* PHY auto-detection alias */
17 * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
18 * as it claims that the MDC clock division is applied to the cpu_1x clock
21 * the PHY", p. 1074, that the MDC clock division is applied to the IOU_SWITCH_CLK.
23 * on the UltraScale compared to the Zynq-7000.
24 * -> Contrary to earlier revisions of this driver, all dividers are available
25 * to both the UltraScale and the Zynq-7000.
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */