Lines Matching +full:phy +full:- +full:clock
6 The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables
7 Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide
8 more flexible power supply options, the ESP32-Ethernet-Kit also supports power
11 .. _get-started-esp32-ethernet-kit-v1.2-overview:
13 ESP32-Ethernet-Kit is an ESP32-WROVER-E based development.
14 For more information, check the datasheet at `ESP32-WROVER-E Datasheet`_.
17 board B. The `Ethernet Board (A)`_ contains Bluetooth/Wi-Fi dual-mode
18 ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet
19 Transceiver (PHY). The `PoE Board (B)`_ provides power over Ethernet
23 .. _get-started-esp32-ethernet-kit-v1.2:
25 .. figure:: img/esp32-ethernet-kit-v1.2.jpg
27 :alt: ESP32-Ethernet-Kit V1.2
28 :figclass: align-center
30 ESP32-Ethernet-Kit V1.2
33 features FTDI FT2232H chip - an advanced multi-interface USB bridge.
41 The block diagram below shows the main components of ESP32-Ethernet-Kit
44 .. figure:: img/esp32-ethernet-kit-v1.1-block-diagram.jpg
46 :alt: ESP32-Ethernet-Kit block diagram
47 :figclass: align-center
49 ESP32-Ethernet-Kit block diagram
53 ----------------------
56 and controls of the ESP32-Ethernet-Kit.
58 .. _get-started-esp32-ethernet-kit-a-v1.2-layout:
64 .. figure:: img/esp32-ethernet-kit-a-v1.2-layout.jpg
66 :alt: ESP32-Ethernet-Kit V1.2
67 :figclass: align-center
69 ESP32-Ethernet-Kit - Ethernet Board (A) layout
74 .. list-table:: Table 1 Component Description
76 :header-rows: 1
78 * - Key Component
79 - Description
80 * - ESP32-WROVER-E
81 - This ESP32 module features 64-Mbit PSRAM for flexible extended storage
83 * - GPIO Header 2
84 - Five unpopulated through-hole solder pads to provide access to selected
86 * - Function Switch
87 - A 4-bit DIP switch used to configure the functionality of selected GPIOs
89 * - Tx/Rx LEDs
90 - Two LEDs to show the status of UART transmission.
91 * - FT2232H
92 - The FT2232H chip serves as a multi-protocol USB-to-serial bridge which
94 ESP32. FT2232H also features USB-to-JTAG interface which is available
95 on channel A of the chip, while USB-to-serial is on channel B.
96 The FT2232H chip enhances user-friendliness in terms of application
97 development and debugging. See `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_
98 * - USB Port
99 - USB interface. Power supply for the board as well as the communication
101 * - Power Switch
102 - Power On/Off Switch. Toggling the switch to **5V0** position powers the
104 * - 5V Input
105 - The 5 V power supply interface can be more convenient when the board is
107 * - 5V Power On LED
108 - This red LED turns on when power is supplied to the board, either from
110 * - DC/DC Converter
111 - Provided DC 5 V to 3.3 V conversion, output current up to 2 A.
112 * - Board B Connectors
113 - A pair male and female header pins for mounting the `PoE Board (B)`_
114 * - IP101GRI (PHY)
115 - The physical layer (PHY) connection to the Ethernet cable is
118 chip. The connection between PHY and ESP32 is done through the reduced
119 media-independent interface (RMII), a variant of the media-independent
120 interface `(MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_
121 standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100
123 * - RJ45 Port
124 - Ethernet network data transmission port.
125 * - Magnetics Module
126 - The Magnetics are part of the Ethernet specification to protect against
130 * - Link/Activity LEDs
131 - Two LEDs (green and red) that respectively indicate the "Link" and
132 "Activity" statuses of the PHY.
133 * - BOOT Button
134 - Download button. Holding down **BOOT** and then pressing **EN**
137 * - EN Button
138 - Reset button.
139 * - GPIO Header 1
140 - This header provides six unpopulated through-hole solder pads connected
160 .. figure:: img/esp32-ethernet-kit-b-v1.0-layout.jpg
162 :alt: ESP32-Ethernet-Kit - PoE Board (B)
163 :figclass: align-center
165 ESP32-Ethernet-Kit - PoE Board (B) layout
167 .. list-table:: Table PoE Board (B)
169 :header-rows: 1
171 * - Key Component
172 - Description
173 * - Board A Connector
174 - Four female (left) and four male (right) header pins for connecting the
178 * - External Power Terminals
179 - Optional power supply (26.6 ~ 54 V) to the PoE Board (B).
181 .. _get-started-esp32-ethernet-kit-v1.2-setup-options:
187 This section describes options to configure the ESP32-Ethernet-Kit hardware.
191 ---------------
207 RMII Clock Selection
208 --------------------
210 The ethernet MAC and PHY under RMII working mode need a common 50 MHz
211 reference clock (i.e. RMII clock) that can be provided either externally,
216 For additional information on the RMII clock selection, please refer to
217 `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_, sheet 2, location D2.
219 RMII Clock Sourced Externally by PHY
222 By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the
223 IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency
224 multiplication of 25 MHz crystal connected to the PHY. For details, please see
227 .. figure:: img/esp32-ethernet-kit-rmii-clk-from-phy.jpg
229 :alt: RMII Clock from IP101GRI PHY
230 :figclass: align-center
232 RMII Clock from IP101GRI PHY
234 Please note that the PHY is reset on power up by pulling the RESET_N signal
236 PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter
237 download mode (when the clock signal of REF_CLK_50M is at a high logic level
238 during the GPIO0 power-up sampling phase).
241 RMII Clock Sourced Internally from ESP32's APLL
244 Another option is to source the RMII Clock from internal ESP32 APLL, see
245 figure below. The clock signal coming from GPIO0 is first inverted, to account
246 for transmission line delay, and then supplied to the PHY.
248 .. figure:: img/esp32-ethernet-kit-rmii-clk-to-phy.jpg
250 :alt: RMII Clock from ESP Internal APLL
251 :figclass: align-center
253 RMII Clock from ESP Internal APLL
257 `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_,
260 RMII clock.
264 ---------------
267 functions of the ESP32-Ethernet-Kit.
270 IP101GRI (PHY) Interface
273 The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table
274 below. Implementation of ESP32-Ethernet-Kit defaults to Reduced
275 Media-Independent Interface (RMII).
278 No. ESP32 Pin (MAC) IP101GRI (PHY)
281 ---------------------------------------
289 ---- ---------------- ---------------
291 ---------------------------------------
294 ---- ---------------- ---------------
295 *PHY Reset*
296 ---------------------------------------
312 ESP32-Ethernet-Kit.
350 ESP32-WROVER-E module and therefore not available for use. If you need
352 e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
360 .. csv-table::
361 :header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments
392 1. To prevent the power-on state of the GPIO0 from being affected by the
393 clock output on the PHY side, the RESET_N signal to PHY defaults to
394 low, turning the clock output off. After power-on you can control
395 RESET_N with GPIO5 to turn the clock output on. See also
396 `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off
397 the clock output through RESET_N, it is recommended to use a crystal
400 turned on by ESP32 after power-up. For a reference design please see
401 `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`_.
404 ESP32-WROVER-E module and therefore not available for use. If you need
406 e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
417 .. code-block:: console
466 .. zephyr-app-commands::
468 :zephyr-app: samples/hello_world
471 :west-args: --sysbuild
480 .. code-block::
495 With ``--sysbuild`` option the bootloader will be re-build and re-flash
517 .. zephyr-app-commands::
518 :zephyr-app: samples/hello_world
523 configuration. Here is an example for the :zephyr:code-sample:`hello_world`
526 .. zephyr-app-commands::
527 :zephyr-app: samples/hello_world
533 .. code-block:: shell
540 .. code-block:: console
542 ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
553 ``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
556 Here is an example for building the :zephyr:code-sample:`hello_world` application.
558 .. zephyr-app-commands::
559 :zephyr-app: samples/hello_world
562 …:gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/s…
564 You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hell…
566 .. zephyr-app-commands::
567 :zephyr-app: samples/hello_world
575 Enable Ethernet MAC, PHY and MDIO; add these to your device tree overlay:
577 .. code-block:: devicetree
583 &phy {
593 .. code-block:: cfg
602 RESET_N (GPIO5) is automatically set high to enable the Ethernet PHY
608 .. target-notes::
610 .. _`ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`: https://dl.espressif.com/dl/schematics/…
611 .. _`ESP32-WROVER-E Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-w…
612 .. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases