Lines Matching +full:phy +full:- +full:clock

3 # Copyright (c) 2016-2017 ARM Ltd
5 # SPDX-License-Identifier: Apache-2.0
36 	  Note, this driver performs one shot PHY setup.
37 	  There is no support for PHY disconnect, reconnect or configuration change.
62 	  - IPv4, UDP and TCP checksum (both Rx and Tx)
113 	  - IPv4, UDP and TCP checksum (both Rx and Tx)
132 	bool "RMII clock from external sources"
134 	  Setting this option will configure MCUX clock block to feed RMII
135 	  reference clock from external source (ENET_1588_CLKIN)
138 	bool "Do not use SMI for PHY communication"
140 	  Some PHY devices, with DSA capabilities do not use SMI for
141 	  communication with MAC ENET controller. Other busses - like SPI
145 	int "PHY poll period (ms)"
149 	  Set the PHY status polling period.
152 	bool "Additional detailed PHY debug"
154 	  Enable additional PHY related debug information related to
155 	  PHY status polling.
158 	bool "Reset the PHY at boot"
160 	  Reset the ethernet PHY at boot. Requires dts properties int-gpios and
161 	  reset-gpios to be present.
164 	bool "MCUX PTP clock driver support"
168 	  Enable MCUX PTP clock support.
173 	int "Frequency of the clock source for the PTP timer"
185 	  MCUX PTP Clock initialization priority level. There is