1 /*
2 * Copyright (c) 2019 Interay Solutions B.V.
3 * Copyright (c) 2019 Oane Kingma
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/init.h>
9 #include "board.h"
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/sys/printk.h>
12 #include "em_cmu.h"
13
efm32gg_stk3701a_init(void)14 static int efm32gg_stk3701a_init(void)
15 {
16 #ifdef CONFIG_ETH_GECKO
17 const struct device *cur_dev;
18
19 /* Enable the ethernet PHY power */
20 cur_dev = DEVICE_DT_GET(ETH_PWR_ENABLE_GPIO_NODE);
21 if (!device_is_ready(cur_dev)) {
22 printk("Ethernet PHY power gpio port is not ready!\n");
23 return -ENODEV;
24 }
25
26 gpio_pin_configure(cur_dev, ETH_PWR_ENABLE_GPIO_PIN, GPIO_OUTPUT);
27 gpio_pin_set(cur_dev, ETH_PWR_ENABLE_GPIO_PIN, 1);
28
29 /* Configure ethernet reference clock */
30 cur_dev = DEVICE_DT_GET(ETH_REF_CLK_GPIO_NODE);
31 if (!device_is_ready(cur_dev)) {
32 printk("Ethernet reference clock gpio port is not ready!\n");
33 return -ENODEV;
34 }
35
36 gpio_pin_configure(cur_dev, ETH_REF_CLK_GPIO_PIN, GPIO_OUTPUT);
37 gpio_pin_set(cur_dev, ETH_REF_CLK_GPIO_PIN, 0);
38
39 CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
40
41 /* enable CMU_CLK2 as RMII reference clock */
42 CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO;
43 CMU->ROUTELOC0 = (CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK) |
44 (ETH_REF_CLK_LOCATION << _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT);
45 CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN;
46
47 /* Release the ethernet PHY reset */
48 cur_dev = DEVICE_DT_GET(ETH_RESET_GPIO_NODE);
49 if (!device_is_ready(cur_dev)) {
50 printk("Ethernet PHY reset gpio port is not ready!\n");
51 return -ENODEV;
52 }
53
54 gpio_pin_configure(cur_dev, ETH_RESET_GPIO_PIN, GPIO_OUTPUT);
55 gpio_pin_set(cur_dev, ETH_RESET_GPIO_PIN, 1);
56 #endif /* CONFIG_ETH_GECKO */
57
58 return 0;
59 }
60
61 /* needs to be done after GPIO driver init */
62 SYS_INIT(efm32gg_stk3701a_init, POST_KERNEL,
63 CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
64
