1/* 2 * Copyright 2022,2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/dts-v1/; 8 9#include <nxp/nxp_mimx93_a55.dtsi> 10#include "imx93_evk-pinctrl.dtsi" 11#include <zephyr/dt-bindings/input/input-event-codes.h> 12 13/ { 14 model = "NXP i.MX93 A55"; 15 compatible = "fsl,mimx93"; 16 17 chosen { 18 zephyr,console = &lpuart2; 19 zephyr,shell-uart = &lpuart2; 20 /* sram node actually locates at DDR DRAM */ 21 zephyr,sram = &dram; 22 zephyr,canbus = &flexcan2; 23 }; 24 25 cpus { 26 cpu@0 { 27 status = "disabled"; 28 }; 29 }; 30 31 dram: memory@d0000000 { 32 reg = <0xd0000000 DT_SIZE_M(1)>; 33 }; 34 35 aliases { 36 led0 = &led_r; 37 led1 = &led_g; 38 sw0 = &btn_1; 39 }; 40 41 leds { 42 compatible = "gpio-leds"; 43 led_r: led_r { 44 label = "LED_R"; 45 gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; 46 }; 47 led_g: led_g { 48 label = "LED_G"; 49 gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; 50 }; 51 led_b: led_b { 52 label = "LED_B"; 53 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 54 }; 55 }; 56 57 keys { 58 compatible = "gpio-keys"; 59 60 btn_1: btn_1{ 61 label = "BTN1"; 62 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; 63 zephyr,code = <INPUT_KEY_0>; 64 }; 65 66 btn_2: btn_2{ 67 label = "BTN2"; 68 gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; 69 zephyr,code = <INPUT_KEY_1>; 70 }; 71 }; 72 73 board_exp_sel: board-exp-sel { 74 /* 75 * Kconfig BOARD_MIMX93_EVK_A55_EXP_SEL_INIT must be 76 * enabled to configure it during init. 77 */ 78 compatible = "imx93evk-exp-sel"; 79 mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>; 80 mux = "A"; 81 }; 82 83 can_phy0: can-phy0 { 84 compatible = "nxp,tja1057", "can-transceiver-gpio"; 85 standby-gpios = <&gpio_exp0 8 GPIO_ACTIVE_HIGH>; 86 max-bitrate = <8000000>; 87 #phy-cells = <0>; 88 status = "okay"; 89 }; 90}; 91 92&enet { 93 status = "okay"; 94}; 95 96&enet_mac { 97 pinctrl-0 = <&pinmux_enet>; 98 pinctrl-names = "default"; 99 phy-handle = <&phy>; 100 zephyr,random-mac-address; 101 phy-connection-type = "rgmii"; 102 status = "okay"; 103}; 104 105&enet_mdio { 106 pinctrl-0 = <&pinmux_mdio>; 107 pinctrl-names = "default"; 108 status = "okay"; 109 phy: phy@2 { 110 compatible = "realtek,rtl8211f"; 111 reg = <2>; 112 status = "okay"; 113 }; 114}; 115 116&lpuart1 { 117 status = "disabled"; 118 current-speed = <115200>; 119 /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ 120 pinctrl-0 = <&uart1_default>; 121 pinctrl-names = "default"; 122}; 123 124&lpuart2 { 125 status = "okay"; 126 current-speed = <115200>; 127 /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ 128 pinctrl-0 = <&uart2_default>; 129 pinctrl-names = "default"; 130}; 131 132 133&lpi2c1 { 134 status = "disabled"; 135 clock-frequency = <I2C_BITRATE_FAST>; 136 pinctrl-0 = <&i2c1_default>; 137 pinctrl-names = "default"; 138}; 139 140&lpi2c2 { 141 status = "okay"; 142 clock-frequency = <I2C_BITRATE_FAST>; 143 pinctrl-0 = <&i2c2_default>; 144 pinctrl-names = "default"; 145 146 mfd0:adp5585@34 { 147 compatible = "adi,adp5585"; 148 reg = <0x34>; 149 status = "okay"; 150 151 gpio_exp0: adp5585_gpio { 152 compatible = "adi,adp5585-gpio"; 153 gpio-controller; 154 #gpio-cells = <2>; 155 ngpios = <13>; 156 gpio-reserved-ranges = <5 3>; 157 status = "okay"; 158 /* 159 * This device has non-contiguous gpio range: 160 * GPIO Pin R0~R4 are gpio0~4 161 * GPIO Pin C0~C4 are gpio8~12 162 */ 163 }; 164 }; 165 166 gpio_exp1: pcal6524@22 { 167 compatible = "nxp,pcal6524"; 168 reg = <0x22>; 169 gpio-controller; 170 #gpio-cells = <2>; 171 ngpios = <24>; 172 int-gpios = <&gpio3 27 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; 173 status = "okay"; 174 }; 175}; 176 177&lpspi3 { 178 status = "disabled"; 179 clock-frequency = <1000000>; 180 pinctrl-0 = <&spi3_default>; 181 pinctrl-names = "default"; 182}; 183 184&gpio1{ 185 status = "okay"; 186}; 187 188&gpio2{ 189 status = "okay"; 190}; 191 192&gpio3{ 193 status = "okay"; 194}; 195 196&gpio4{ 197 status = "okay"; 198}; 199 200&flexcan2 { 201 pinctrl-0 = <&flexcan2_default>; 202 pinctrl-names = "default"; 203 phys = <&can_phy0>; 204 status = "okay"; 205}; 206