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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/
D_soc_inthandlers.h6 #include <xtensa/config/core-isa.h>
11 #error core-isa.h interrupt level does not match dispatcher!
14 #error core-isa.h interrupt level does not match dispatcher!
17 #error core-isa.h interrupt level does not match dispatcher!
20 #error core-isa.h interrupt level does not match dispatcher!
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/dts/riscv/qemu/
Dvirt-riscv32.dtsi14 riscv,isa = "rv32gc";
18 riscv,isa = "rv32gc";
22 riscv,isa = "rv32gc";
26 riscv,isa = "rv32gc";
30 riscv,isa = "rv32gc";
34 riscv,isa = "rv32gc";
38 riscv,isa = "rv32gc";
42 riscv,isa = "rv32gc";
Dvirt-riscv64.dtsi14 riscv,isa = "rv64gc";
18 riscv,isa = "rv64gc";
22 riscv,isa = "rv64gc";
26 riscv,isa = "rv64gc";
30 riscv,isa = "rv64gc";
34 riscv,isa = "rv64gc";
38 riscv,isa = "rv64gc";
42 riscv,isa = "rv64gc";
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/
D_soc_inthandlers.h18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/nxp/imx/imx8/adsp/
D_soc_inthandlers.h18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/
D_soc_inthandlers.h18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/
D_soc_inthandlers.h18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/espressif/common/include/
D_soc_inthandlers.h19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
48 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/cdns/sample_controller32/include/
D_soc_inthandlers.h19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
48 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
D_soc_inthandlers.h17 #include <xtensa/config/core-isa.h>
22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
43 #error core-isa.h interrupt level does not match dispatcher!
46 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/cdns/xtensa_sample_controller/include/
D_soc_inthandlers.h13 #include <xtensa/config/core-isa.h>
17 #error core-isa.h interrupt level does not match dispatcher!
20 #error core-isa.h interrupt level does not match dispatcher!
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/samples/subsys/llext/modules/
Dsample.yaml4 - qemu_cortex_a9 # ARM Cortex-A9 (ARMv7-A ISA)
5 - qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA)
6 - qemu_cortex_a53 # ARM Cortex-A53 (ARMv8-A ISA)
7 - mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA)
8 - mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA)
/Zephyr-latest/tests/subsys/llext/
Dtestcase.yaml12 - qemu_cortex_a9 # ARM Cortex-A9 (ARMv7-A ISA)
13 - qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA)
14 - mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA)
15 - mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA)
57 - qemu_cortex_a53 # ARM Cortex-A53 (ARMv8-A ISA)
68 - qemu_xtensa/dc233c # Xtensa ISA
85 - qemu_xtensa/dc233c # Xtensa ISA
101 - qemu_xtensa/dc233c # Xtensa ISA
119 - qemu_xtensa/dc233c # Xtensa ISA
/Zephyr-latest/soc/intel/intel_adsp/ace/
D_soc_inthandlers.h16 #include <xtensa/config/core-isa.h>
21 #error core-isa.h interrupt level does not match dispatcher!
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
/Zephyr-latest/soc/andestech/ae350/
DKconfig25 prompt "Base CPU ISA options"
29 bool "RISCV32 CPU ISA"
35 bool "RISCV32E CPU ISA"
41 bool "RISCV64 CPU ISA"
67 bool "AndeStar V5 DSP ISA"
/Zephyr-latest/soc/neorv32/
DKconfig19 # NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
31 bool "RISC-V ISA Extension \"C\""
34 Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
DKconfig.soc9 The NEORV32 CPU implementation must have the following RISC-V ISA
14 The following NEORV32 CPU ISA extensions are not currently supported
/Zephyr-latest/doc/hardware/arch/
Drisc-v.rst13 ISA extensions as well as :ref:`semihosting<semihost_guide>`.
22 ISA extensions
25 It's possible to set in Zephyr which ISA extensions (RV32/64I(E)MAFD(G)QC)
27 kconfig. Look at :file:`arch/riscv/Kconfig.isa` for more information.
/Zephyr-latest/arch/xtensa/core/
DCMakeLists.txt45 # -dM, supported by all Xtensa toolchains) core-isa.h file available
46 # as "core-isa-dM.h". This can be easily parsed by non-C tooling.
49 # are the official places where we find core-isa.h. (Also that we
52 set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM.h)
53 set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
54 file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
65 # THREADPTR is in core-isa.h which can be parsed in gen_zsr.py.
Dxtensa_intgen.tmpl1 #include <xtensa/config/core-isa.h>
9 * available per-hardware by an SDK-provided core-isa.h file.
Dxtensa_intgen.py5 # Pass an Xtensa core-isa.h file on stdin or the command line, emits a
95 # Re-include the core-isa header and be sure our definitions match, for sanity
96 cprint("#include <xtensa/config/core-isa.h>")
104 cprint("#error core-isa.h interrupt level does not match dispatcher!")
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu740.dtsi38 riscv,isa = "rv64imac_zicsr_zifencei";
53 riscv,isa = "rv64gc";
67 riscv,isa = "rv64gc";
81 riscv,isa = "rv64gc";
95 riscv,isa = "rv64gc";
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi23 riscv,isa = "rv32gc_xandes";
40 riscv,isa = "rv32gc_xandes";
57 riscv,isa = "rv32gc_xandes";
74 riscv,isa = "rv32gc_xandes";
91 riscv,isa = "rv32gc_xandes";
108 riscv,isa = "rv32gc_xandes";
125 riscv,isa = "rv32gc_xandes";
142 riscv,isa = "rv32gc_xandes";
/Zephyr-latest/dts/riscv/starfive/
Djh7110-visionfive-v2.dtsi26 riscv,isa = "rv64imac_zicsr_zifencei";
51 riscv,isa = "rv64imafdcg";
76 riscv,isa = "rv64imafdcg";
101 riscv,isa = "rv64imafdcg";
126 riscv,isa = "rv64imafdcg";
/Zephyr-latest/include/zephyr/arch/arc/asm-compat/
Dassembler.h7 * Top level include file providing ISA pseudo-mnemonics for use in assembler
11 * e.g. "LDR" maps to 'LD' on 32-bit ISA, 'LDL' on 64-bit ARCv2/ARC64

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